MPC8280 datasheet(124/1386 Pages) FREESCALE

124 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-8

Freescale Semiconductor

2.2.6.1

Memory Management Units (MMUs)

The processor core’s MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gbytes (232) of

physical memory (referred to as real memory in the PowerPC architecture specification) for instructions

and data. The MMUs also control access privileges for these spaces on block and page granularities.

Referenced and changed status is maintained by the processor for each page to assist implementation of a

demand-paged virtual memory system. A key bit is implemented to provide information about memory

protection violations prior to page table search operations.

The LSU calculates effective addresses for data loads and stores, performs data alignment to and from

cache memory, and provides the sequencing for load and store string and multiple word instructions. The

instruction unit calculates the effective addresses for instruction fetching.

The MMUs translate effective addresses and enforce the protection hierarchy programmed by the

operating system in relation to the supervisor/user privilege level of the access and in relation to whether

the access is a load or store.

2.2.6.2

Cache Units

The processor core provides independent 16-Kbyte, four-way set-associative instruction and data caches.

The cache block size is 32 bytes. The caches are designed to adhere to a write-back policy, but the

processor core allows control of cacheability, write policy, and memory coherency at the page and block

levels. The caches use a least recently used (LRU) replacement algorithm.

The load/store and instruction fetch units provide the caches with the address of the data or instruction to

be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.

2.3

Programming Model

The following subsections describe the PowerPC instruction set and addressing modes.

2.3.1

This section describes the register organization in the processor core as defined by the three programming

environments of the PowerPC architecture—the user instruction set architecture (UISA), the virtual

environment architecture (VEA), and the operating environment architecture (OEA), as well as the G2_LE

core implementation-specific registers. Full descriptions of the basic register set defined by the PowerPC

architecture are provided in Chapter 2 in The Programming Environments Manual.

The PowerPC architecture defines register-to-register operations for all arithmetic instructions. Source

data for these instructions is accessed from the on-chip registers or is provided as an immediate value

embedded in the opcode. The three-register instruction format allows specification of a target register

distinct from the two source registers, thus preserving the original data for use by other instructions and

reducing the number of instructions required for certain operations. Data is transferred between memory

and registers with explicit load and store instructions only.

Figure 2-2 shows the complete MPC8280 register set and the programming environment to which each

MPC8280 датащи(PDF) 124 Page - Freescale Semiconductor, Inc

MPC8280 датащи(HTML) 124 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL