MPC8280 datasheet(120/1386 Pages) FREESCALE

120 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-4

Freescale Semiconductor

•

Five independent execution units and two register files

— BPU featuring static branch prediction

— A 32-bit IU

— Fully IEEE 754–compliant FPU for both single- and double-precision operations

— LSU for data transfer between data cache and GPRs and FPRs

— SRU that executes condition register (CR), special-purpose register (SPR), and integer

add/compare instructions

— Thirty-two GPRs for integer operands

— Thirty-two FPRs for floating-point operands. They also can be used for general operands using

floating-point load and store operations.

•

High instruction and data throughput

— Zero-cycle branch capability (branch folding)

— Programmable static branch prediction on unresolved conditional branches

— BPU that performs CR lookahead operations

— Instruction fetch unit capable of fetching two instructions per clock from the instruction cache

— A six-entry instruction queue that provides lookahead capability

— Independent pipelines with feed-forwarding that reduces data dependencies in hardware

— 16-Kbyte data cache—Four-way set-associative, physically addressed; LRU replacement

algorithm

— 16-Kbyte instruction cache—Four-way set-associative, physically addressed; LRU

replacement algorithm

— Cache write-back or write-through operation programmable on a per page or per block basis

— Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte

segment size

— A 64-entry, two-way set-associative ITLB

— A 64-entry, two-way set-associative DTLB

— Eight-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks

— Software table search operations and updates supported through fast trap mechanism

— 52-bit virtual address; 32-bit physical address

•

Facilities for enhanced system performance

— A 32- or 64-bit, split-transaction external data bus with burst transfers

— Support for one-level address pipelining and out-of-order bus transactions

— Critical interrupt exception support

— Hardware support for misaligned little-endian accesses

•

Integrated power management

— One power-saving mode: doze

— Automatic dynamic power reduction when internal functional units are idle

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