MPC8280 datasheet(119/1386 Pages) FREESCALE

119 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-3

The processor core is a superscalar processor that can issue and retire as many as three instructions per

clock. Instructions can execute out of order for increased performance; however, the processor core makes

completion appear sequential.

The processor core integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a

branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to

execute five instructions in parallel and the use of simple instructions with rapid execution times yield high

efficiency and throughput. Most integer instructions execute in one clock cycle. On the processor core, the

FPU is pipelined so a single-precision multiply-add instruction can be issued and completed every clock

cycle. The processor core provides hardware support for all single- and double-precision floating-point

operations for most value representations and all rounding modes.

The processor core supports integer data types of 8, 16, and 32 bits, and floating-point data types of 32 and

64 bits. The 32 architecturally-defined floating point registers (FPRs) can be used to hold 32, 64-bit

operands that can in turn be transferred to and from the 32 general-purpose registers (GPRs), which can

hold 32, 32-bit operands.

The processor core provides separate on-chip, 16-Kbyte, four-way set-associative, physically addressed

caches for instructions and data and on-chip instruction and data memory management units (MMUs). The

MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers

(DTLB and ITLB) that provide support for demand-paged virtual memory address translation and

variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement

algorithm. The processor core also supports block address translation through the use of two independent

instruction and data block address translation (IBAT and DBAT) arrays of eight entries each. Effective

addresses are compared simultaneously with all eight entries in the BAT array during block translation. In

accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the

BAT translation takes priority.

As an added feature to the MPC603e core, the MPC8280 can lock the contents of 1–3 ways in the

instruction and data cache (or an entire cache). For example, this allows embedded applications to lock

interrupt routines or other important (time-sensitive) instruction sequences into the instruction cache. It

allows data to be locked into the data cache, which may be important to code that must have deterministic

execution.

The processor core has a 60x bus that incorporates a 64-bit data bus and a 32-bit address bus. The processor

core supports single-beat and burst data transfers for memory accesses and supports memory-mapped I/O

operations.

2.2

G2_LE Core Features

This section describes the major features of the processor core:

•

High-performance, superscalar microprocessor

— As many as three instructions issued and retired per clock cycle

— As many as four instructions in execution per clock cycle

— Single-cycle execution for most instructions

— Pipelined FPU for all single-precision and most double-precision operations

MPC8280 датащи(PDF) 119 Page - Freescale Semiconductor, Inc

MPC8280 датащи(HTML) 119 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL