MPC8280 datasheet(268/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

7-10

Freescale Semiconductor

7.2.5.1.2

Address Acknowledge (AACK)—Input

Following are the state meaning and timing comments for AACK as an input signal.

State Meaning

Asserted—Indicates that a 60x bus slave is terminating the address tenure. On the

cycle following the assertion of AACK, the bus master releases the address tenure

related signals to the high-impedance state and samples ARTRY.

Negated—Indicates that the address tenure must remain active and the address

tenure related signals driven.

Timing Comments

Assertion—Occurs during the 60x bus slave access, at least two clocks after TS.

Negation—Occurs one clock after assertion.

7.2.5.2

Address Retry (ARTRY)

The address retry (ARTRY) signal is both an input and output signal on the MPC8280.

7.2.5.2.1

Address Retry (ARTRY)—Output

Following are the state meaning and timing comments for ARTRY as an output signal.

State Meaning

Asserted—Indicates that the MPC8280 detects a condition in which an address

tenure must be retried. If the MPC8280 processor needs to update memory as a

result of snoop that caused the retry, the MPC8280 asserts BR the second cycle

after AACK if ARTRY is asserted.

High Impedance—Indicates that the MPC8280 does not need the address tenure

to be retried.

Timing Comments

Assertion—Asserted the third bus cycle following the assertion of TS if a retry is

required.

Negation—Occurs the second bus cycle after the assertion of AACK. Since this

signal may be simultaneously driven by multiple devices, it negates in a unique

fashion. First the buffer goes to high impedance for a minimum of one-half

processor cycle (dependent on the clock mode), then it is driven negated for one

bus cycle before returning to high impedance.

7.2.5.2.2

Address Retry (ARTRY)—Input

Following are the state meaning and timing comments for the ARTRY input.

State Meaning

Asserted—If the MPC8280 is the address bus master, ARTRY indicates that the

MPC8280 must retry the preceding address tenure and immediately negate BR (if

asserted). If the associated data tenure has started, the MPC8280 also aborts the

data tenure immediately even if the burst data has been received. If the MPC8280

is not the address bus master, this input indicates that the MPC8280 should negate

BR for one bus clock cycle immediately after external device asserts ARTRY to

permit a copy-back operation to main memory. Note that the subsequent address

presented on the address bus may not be the one that generated the assertion of

ARTRY.

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