MPC8280 datasheet(265/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

7-7

7.2.3.1.2

Address Bus (A[0–31])—Input

Following are the state meaning and timing comments for the A[0–31] input signals.

State Meaning

Asserted—Indicates that another device has begun a bus transaction and that the

address bus and transfer attribute signals are valid for snooping and in slave mode.

Negated—Has no special meaning.

Timing Comments

Assertion/Negation—Must be valid on the same cycle that TS is asserted; sampled

by the processor only on this cycle.

7.2.4

Address Transfer Attribute Signals

In internal only mode the address transfer attribute signals have no meaning.

The transfer attribute signals are a set of signals that further characterize the transfer—such as the size of

the transfer, whether it is a read or write operation, and whether it is a burst or single-beat transfer. For a

detailed description of how these signals interact, see Section 7.2.4, “Address Transfer Attribute Signals.”

7.2.4.1

Transfer Type (TT[0–4])

The transfer type signals (TT[0–4]) consist of five input/output signals on the MPC8280. For a complete

description of TT[0–4] signals and transfer type encoding, see Section 8.4.3.1, “Transfer Type Signal

(TT[0–4]) Encoding.”

7.2.4.1.1

Transfer Type (TT[0–4])—Output

Following are the state meaning and timing comments for the TT[0–4] output signals on the MPC8280.

State Meaning

Asserted/Negated—Specifies the type of transfer in progress.

Timing Comments

Assertion/Negation—Same as A[0–31].

High Impedance—Same as A[0–31].

7.2.4.1.2

Transfer Type (TT[0–4])—Input

Following are the state meaning and timing comments for the TT[0–4] input signals on the MPC8280.

State Meaning

Asserted/Negated—Specifies the type of transfer in progress for snooping by the

MPC8280.

Timing Comments

Assertion/Negation—Same as A[0–31].

7.2.4.2

Transfer Size (TSIZ[0–3])

The transfer size (TSIZ[0–3]) signals consist of four input/output signals on the MPC8280, following are

the state meaning and timing comments for the TSIZ[0–3] signals on the MPC8280.

State Meaning

Asserted/Negated—Specifies the data transfer size for the transaction (see

Section 8.4.3.3, “TBST and TSIZ[0–3] Signals and Size of Transfer”). During

graphics transfer operations, these signals form part of the Resource ID (see

TBST).

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