MPC8280 datasheet(264/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

7-6

Freescale Semiconductor

request if the transfer attributes TT[0–4] indicate that a data tenure is required for

the transaction.

Negated—Has no special meaning during a normal transaction.

Timing Comments

Assertion/Negation—Driven and asserted on the cycle after a qualified BG is

accepted by MPC8280; remains asserted for one clock only. Negated for the

remainder of the address tenure. Assertion is coincident with the first clock that

ABB is asserted.

High Impedance—Occurs the cycle following the assertion of AACK (same cycle

as ABB negation).

7.2.2.2

Transfer Start (TS)—Input

Following are the state meaning and timing comments for the TS input signal.

State Meaning

Asserted—Indicates that another device has begun a bus transaction and that the

address bus and transfer attribute signals are valid for snooping.

Negated—Has no special meaning.

Timing Comments

Assertion/Negation—Must be asserted for one cycle only and then immediately

negated. Assertion may occur at any time during the assertion of ABB.

7.2.3

Address Transfer Signals

In internal only mode the memory controller uses these signals for glueless address transfers to memory

and I/O devices.

The address transfer signals are used to transmit the address.

7.2.3.1

Address Bus (A[0–31])

The address bus (A[0–31]) consists of 32 signals that are both input and output signals.

7.2.3.1.1

Address Bus (A[0–31])—Output

Following are the state meaning and timing comments for the A[0–31] output signals.

State Meaning

Content—Specifies the physical address of the bus transaction. For burst or

extended operations, the address is a double-word.

Timing Comments

Assertion/Negation—Driven valid on the same cycle that TS is driven/asserted;

remains driven/valid for the duration of the address tenure.

High Impedance— Occurs the cycle following the assertion of AACK; no

precharge action performed on release.

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