MPC8280 datasheet(271/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

7-13

7.2.7.1

Data Bus (D[0–63])

The data bus (D[0–63]) states have the same meanings in both internal only mode external master mode.

The data bus consists of 64 signals that are both inputs and outputs on the MPC8280. Following are the

state meaning and timing comments for the data bus.

State Meaning

The data bus holds 8 byte lanes assigned as shown in Table 7-2.

Timing Comments

The number of times the data bus is driven depends on the transfer size, port size,

and whether the transfer is a single-beat or burst operation.

7.2.7.1.1

Data Bus (D[0–63])—Output

Following are the state meaning and timing comments for the D[0–63] output signals.

State Meaning

Asserted/Negated—Represents the state of data during a data write. Byte lanes not

selected for data transfer do not supply valid data. MPC8280 duplicates data to

enable valid data to be sent to different port sizes.

Timing Comments

Assertion/Negation—Initial beat coincides with DBB, for bursts, transitions on

the bus clock cycle following each assertion of TA and, for port size, transitions

on the bus clock cycle following each assertion of PSDVAL.

High Impedance—Occurs on the bus clock cycle after the final assertion of TA,

TEA, or certain ARTRY cases.

7.2.7.1.2

Data Bus (D[0–63])—Input

Following are the state meaning and timing comments for the D[0–63] input signals.

State Meaning

Asserted/Negated—Represents the state of data during a data read transaction.

Timing Comments

Assertion/Negation—Data must be valid on the same bus clock cycle that TA

and/or PSDVAL is asserted.

7.2.7.2

Data Bus Parity (DP[0–7])

The eight data bus parity (DP[0–7]) signals both output and input signals.

Table 7-1. Data Bus Lane Assignments

Data Bus Signals

Byte Lane

D0–D7

D8–D15

D16–D23

D24–D31

D32–D39

D40–D47

D48–D55

D56–D63

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