MPC8280 datasheet(262/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

7-4

Freescale Semiconductor

a snoop copyback; may also be negated if the external master cancels a bus request

internally before receiving a qualified BG.

High Impedance—Occurs during a hard reset or checkstop condition.

7.2.1.2

Bus Grant (BG)

The address bus grant (BG) signal is both an input and an output signal.

7.2.1.2.1

Bus Grant (BG)—Input

The following are the state meaning and timing comments for the BG signal input.

State Meaning

Asserted—Indicates that the MPC8280 may, with the proper qualification, begin

a bus transaction and assume ownership of the address bus. A qualified bus grant

is generally determined from the bus state as follows: QBG = BG • ¬ABB •

¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that

the assertion of BR is not required for a qualified bus grant (for bus parking).

Negated—Indicates that the MPC8280 is not granted next address ownership.

Timing Comments

Assertion—May occur on any cycle. Once the MPC8280 has assumed address bus

ownership, it does not begin checking for BG again until the cycle after AACK.

Negation—May occur whenever the MPC8280 must be prevented from using the

address bus. The MPC8280 may still assume address bus ownership on the cycle

BG is negated if it was asserted the previous cycle with other bus grant

qualifications.

7.2.1.2.2

Bus Grant (BG)—Output

Following are the state meaning and timing comments for the BG signal output.

State Meaning

Asserted—Indicates that the external device may, with the proper qualification,

begin a bus transaction and assume ownership of the address bus. A qualified bus

grant is generally determined from the bus state as follows: QBG = BG • ¬ABB

• ¬ARTRY where ARTRY is asserted only during the cycle after AACK. Note that

the assertion of BR is not required for a qualified bus grant (for bus parking).

Negated—Indicates that the external device is not granted next address

ownership.

Timing Comments

Assertion—May occur on any cycle. Once the external device has assumed

address bus ownership, it does not begin checking for BG again until the cycle

after AACK.

Negation—May occur when an external device must be kept from using the

address bus. The external device may still assume address bus ownership on the

cycle that BG is negated if it was asserted the previous cycle with other bus grant

qualifications.

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