HT45RM03 datasheet(27/54 Pages) HOLTEK

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HT45RM03

Rev. 1.10

February 16, 2007

ACS2

ACS1

ACS0

Analog Channel

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Analog Input Channel Selection

Bit1 and bit0 of the ACSR register are used to select the A/D clock source.

When the A/D conversion has completed, the EOCB bit will be cleared. The EOCB bit is set to

²1² when the START bit

is set from

²0² to ²1².

Important Note for A/D initialization:

Special care must be taken to initialize the A/D converter each time the Port B A/D channel selection bits are modified,

otherwise the EOCB flag may be in an undefined condition. An A/D initialization is implemented by setting the START

bit high and then clearing it to zero within 10 instruction cycles of the Port B channel selection bits being modified. Note

that if the Port B channel selection bits are all cleared to zero then an A/D initialization is not required.

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

ADRL

¾¾¾¾¾¾¾

ADRH

Note:

D0~D8 is A/D conversion result data bit LSB~MSB.

ADRL (20H), ADRH (21H) Register

The following two programming examples illustrate how to setup and implement an A/D conversion. In the example,

the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.

Example: using EOCB Polling Method to detect end of conversion

mov

a,00000001B

mov

ACSR,a

; setup the ACSR register to select fSYS/8 as the A/D clock

mov

a,00100000B

; setup ADCR register to configure Port PB0~PB3 as A/D inputs

mov

ADCR,a

; and select AN0 to be connected to the A/D converter

; As the Port B channel bits have changed the following START

; signal (0-1-0) must be issued within 10 instruction cycles

Start_conversion:

clr

START

set

START

; reset A/D

clr

START

; start A/D

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