HT45RM03 datasheet(19/54 Pages) HOLTEK

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HT45RM03

Rev. 1.10

February 16, 2007

It is recommended that unused or not bonded out I/O lines should be set as output pins by software instruction to avoid

consuming power under input floating state.

V D D

O P 0 ~ O P 7

I N T 0 A f o r P A 4 O n l y

I N T 0 B f o r P A 5 O n l y

I N T 0 C f o r P A 6 O n l y

I N T 1 f o r P A 7 O n l y

T M R 0 / T M R 1 f o r P B 7 O n l y

S y s t e m W a k e - u p

( P A o n l y )

R e a d D a t a R e g i s t e r

P C 0 / P C 1 / P C 2 / P C 3 / P C 4 / P C 5 / P D 0

P W M 0 / P W M 0 / P W M 1 / P W M 1 / P W M 2 / P W M 2 / P F D

C o n t r o l B i t P u l l - h i g h

D a t a B u s

W r i t e C o n t r o l R e g i s t e r

C h i p R e s e t

R e a d C o n t r o l R e g i s t e r

W r i t e D a t a R e g i s t e r

D a t a B i t

P A 0 / O P V I N P

P A 1 / C V I N P

P A 2 / C V I N N

P A 3 / C O U T

P A 4 / I N T 0 A

P A 5 / I N T 0 B

P A 6 / I N T 0 C

P A 7 / I N T 1

P B 0 / A N 0 ~ P B 1 / A N 1

P B 2 / A N 2 / O P O U T

P B 3 / A N 3 / O P V I N N

P B 4 / A N 4 ~ P B 6 / A N 6

P B 7 / A N 7 / T M R 0 / T M R 1

P C 0 / P W M 0

P C 1 / P W M 0

P C 2 / P W M 1

P C 3 / P W M 1

P C 4 / P W M 2

P C 5 / P W M 2

P D 0 / P F D

C K

Input/Output Ports

PWM

The microcontroller is provided with three channel PWM

and Complementary PWM output shared with

PC0~PC5, named PWM0~PWM2 and PWM0~PWM2,

with standard 10 bits output, (9+1), (8+2), or (7+3) mode

(configuration option determined). The PWM function

provides output with a varied frequency and duty cycle

by setting particular values into PWMC and PWML,

PWMH registers. The frequency source of the PWM

counter comes from fPWM. The fPWM clock source can be

chosen from fSYS~fSYS/8 (software option determined).

The PWM channel has their data registers denoted as

PWMH (1AH) and PWML (1BH). These two registers

define the PWM output duty cycle. The PWMH is an

8-bit register, and it is a higher-order data register, the

PWML is a lower-order register and two bits (bit1~bit0)

are provided in this register. The PWM duty cycle is

specified by writing to these two PWM data registers,

writing PWML will only put the written data to an internal

lower-order byte buffer (2-bit) and writing PWMH will

transfer the specified data and the contents of the

lower-order byte buffer to PWMH and PWML registers,

respectively. Once the PC0~PC5 is selected as the

PWM and Complementary PWM outputs and the output

function of PC0~PC5 is enabled (PCC.0 ~ PCC.5 =

²0²),

writing

²1² to PC0, PC2 and PC4 register will enable the

PWM output function and writing

²0² will force the PC0,

PC2 and PC4 stay at inactive state (

²0² if the PWMLEV

option is select active high). Writing

²1² to PC1, PC3 and

PC5 register will enable the Complementary PWM out-

put function and writing

²0² will force the PC1, PC3 and

PC5 stay at inactive state (

²0² if the PWMCLEV option is

select active high).

The PWM clock source can be chosen form fSYS~fSYS/8

(dependent on software option). When the fPWM clock

source is selected from fSYS~fSYS/8, the PWM function

provides with a fixed frequency output (fSYS/1024~

(fSYS/8192). The PWM output provides standard 10-bit,

(9+1), (8+2) and (7+3) output mode, it

¢s duty cycle is de-

cided by writing to the PWMH and PWML registers, the

waveform of PWM output is as shown.

When the PWM output function is enabled (writing

²1² to

PC0~PC5 register, when PWM and Complementary

PWM output function is enable) and the fPWM clock

source is selected from PWM prescaler, the value of

PWMPSC0~PWMPSC1, PWML and PWMH can be

written to at any time even if the PWM and Complemen-

tary PWM output is running.

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