HT45RM03 datasheet(18/54 Pages) HOLTEK

18 / 54 page

HT45RM03

Rev. 1.10

February 16, 2007

There is a PWM function shared with PC0~PC5. If the

PWM function is enabled, the PWM0~PWM2 and

PWM0~PWM2 signal will appear on PC0, PC2, PC4

and PC1, PC3, PC5 respectively (if PC0/PC1/PC2/PC3/

PC4/PC5 is operating in output mode).

Writing

²1² to PC0/PC2/PC4 data register will enable

the PWM0/PWM1/PWM2 output function and writing

²0² will force the PC0/PC2/PC4 to remain at ²0² (inac-

tive state). Writing

²1² to PC1/PC3/PC5 data register will

enable the PWM0/PWM1/PWM2 output function and

writing

²0² will force the PC1/PC3/PC5 to remain at ²0²

inactive state). The I/O functions of PC0~PC5 are as

shown.

PWMEN

PC7

PC6

PC4

PC2

PC0

Logical

PWM

Logical

PWM

Logical

PWM

Logical

PWM

PC0, PC2, PC4 Output Function

PWMCEN

PC7

PC6

PC5

PC3

PC1

Logical

PWM

Logical

PWM

Logical

PWM

Logical

PWM

PC1, PC3, PC5 Output Function

There is only one channel PWM and PWM output at a time. The PC.6 and PC.7 is to determine which PWM0/PWM0,

PWM1/PWM1 or PWM2/PWM2 appeared to the PC0/PC1, PC2/PC3 or PC4/PC5.

PC7, PC6

PWM (PWMEN=1)

PWM (PWMCEN=1)

0, 0

PC0/PWM0 is PWM output, if the PC0 is output

mode (PCC.0 =

²0²). The PC2 and PC4 are the

GPIO. Writing

²1² to PC0 data register will enable

the PWM0 output function and writing

²0² will force

the PC0 to remain at PWM0 output inactive state.

PC1/PWM0 is PWM output, if the PC1 is output

mode (PCC.1 =

²0²). The PC3 and PC5 are the

GPIO. Writing

²1² to PC1 data register will enable

the PWM0 output function and writing

²0² will force

the PC1 to remain at PWM0 output inactive state.

0, 1

PC2/PWM1 is PWM output, if the PC2 is output

mode (PCC.2 =

²0²). The PC0 and PC4 are the

GPIO. Writing

²1² to PC2 data register will enable

the PWM1 output function and writing

²0² will force

the PC2 to remain at PWM1 output inactive state.

PC3/PWM1 is PWM output, if the PC3 is output

mode (PCC.3 =

²0²). The PC1 and PC5 are the

GPIO. Writing

²1² to PC3 data register will enable

the PWM1 output function and writing

²0² will force

the PC3 to remain at PWM1 output inactive state.

1, 0

PC4/PWM2 is PWM output, if the PC4 is output

mode (PCC.4 =

²0²). The PC0 and PC2 are the

GPIO. Writing

²1² to PC4 data register will enable

the PWM2 output function and writing

²0² will force

the PC4 to remain at PWM2 output inactive state.

PC5/PWM2 is PWM output, if the PC5 is output

mode (PCC.5 =

²0²). The PC1 and PC3 are the

GPIO. Writing

²1² to PC5 data register will enable

the PWM2 output function and writing

²0² will force

the PC5 to remain at PWM2 output inactive state.

1, 1

PC0/PWM0, PC2/PWM1 and PC4/PWM2 are

PWM output, if the PC0, PC2 and PC4 are output

mode (PCC.0, 2, 4 =

²0²). Writing ²1² to

PC0/PC2/PC4 data register will enable the

PWM0/PWM1/PWM2 output function and writing

²0² will force the PC0/PC2/PC4 to remain at PWM

output inactive state.

PC1/PWM0, PC3/PWM1 and PC5/PWM2 are

PWM output, if the PC1, PC3 and PC5 are output

mode (PCC.1, 3, 5 =

²0²). Writing ²1² to

PC1/PC3/PC5 data register will enable the

PWM0/PWM1/PWM2 output function and writing

²0² will force the PC1/PC3/PC5 to remain at PWM

output inactive state.

Note:

If PWMEN=0, the PWM function output is disable and the PC0, PC2 and PC4 are the GPIO.

If PWMCEN=0, the PWM function output is disable and the PC1, PC3 and PC5 are the GPIO.

The PWMEN and PWMCEN are independent to enable or disable the PWM and PWM Complement function.

If the PCC.x is

²1², the PC.x is input mode. ²x² is from 0~5.

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