HT45RM03 datasheet(17/54 Pages) HOLTEK

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HT45RM03

Rev. 1.10

February 16, 2007

Input/Output Ports

There are 23 bidirectional input/output lines in the

microcontroller, labeled as PA, PB, PC and PD, which

are mapped to the data memory of [12H], [14H], [16H]

and [18H] respectively. All of these I/O ports can be

used for input and output operations. For input opera-

tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

² (m=12H, 14H, 16H or 18H). For output operation,

all the data is latched and remains unchanged until the

output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS output or schmitt trig-

ger input with or without pull-high resistor structures can

be reconfigured dynamically (i.e. on-the-fly) under soft-

ware control. To function as an input, the corresponding

latch of the control register must write

²1². The input

source also depends on the control register. If the con-

trol register bit is

²1², the input will read the pad state. If

the control register bit is

²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, 17H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. The highest 7-bit of port D are not physically im-

plemented; on reading them a

²0² is returned whereas

writing then results in a no-operation. See Application

note.

Each I/O port has a pull-high option. Once the pull-high

option is selected, the I/O port has a pull-high resistor,

otherwise, there

¢s none. Take note that a non-pull-high

I/O port operating in input mode will cause a floating

state.

The PD0 is pin-shared with the PFD signal. If the PFD

function is selected, the output signal in output mode of

PD0 will be the PFD signal generated by the timer/event

counter overflow signal. The input mode is always re-

maining its original functions. Once the PFD option is

selected, the PFD output signal is controlled by PD0

data register only. Writing

²1² to PD0 data register will

enable the PFD output function and writing

²0² will force

the PD0 to remain at

²0². The I/O functions of PD0 are

shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PD0

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

The PA4, PA5, PA6, PA7 and PB7 are pin-shared with

INT0A, INT0B, INT0C, INT1 and TMR0/TMR1 pins re-

spectively. The CVINN and COUT are pin-shared with

PA1, PA2 and PA3. Once the Comparator function is

used, the internal registers related to PA1, PA2 cannot

be used, PA3 can be used as input only (if the COUTEN

²1²), and the PA1, PA2 I/O function, PA3 output func-

tion and pull-high resistor are disabled automatically(if

the COUTEN is

²1²). Once the Comparator function is

used, the PA3 is the GPIO when the COUTEN is

²0².

Software instructions determine the Comparator func-

tion to be used.

CMPEN COUTEN

PA1, PA2, PA3

PA1, PA2, PA3 is GPIO

PA1, PA2 is Comparator input pin

and PA3 is GPIO. PA3 falling

edge can generate the

Comparator interrupt.

PA1, PA2 is comparator input pin

and PA3 is Comparator output

pin. PA3 can read the

Comparateor output status.

The OPVINP, OPVINN and OPOUT are pin-shared with

PA0, PB3/AN3 and PB2/AN2 respectively. Once the

OPA function is used, the internal registers related to

PA0, PB3 and PB2 cannot be used, and the I/O function

and pull-high resistor are disabled automatically. Soft-

ware instructions determine the OPA function to be

used.

OPAEN

PA0, PB3/AN3, PB2/AN2

PA0 is GPIO and PB2/AN2, PB3/AN3 is

GPIO or analog ADC input by ADCR regis-

ter.

PA0, PB3/AN3 is OPA input pin and

PB2/AN2 is OPA output pin. The PB2/AN2

and PB3/AN3 can be analog ADC input if

the related ADC function is enabled.

The PB can also be used as A/D converter inputs. The

A/D function will be described later. Once a PB line is se-

lected as an A/D input (by using software control), the

I/O function and pull-high resistor are disabled automati-

cally.

The PWM0~PWM2 and PWM0~PWM2 output function

are pin-shared with PC0, PC2, PC4 and PC1, PC3, PC5

respectively by software control.

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