HT45RM03 datasheet(12/54 Pages) HOLTEK

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HT45RM03

Rev. 1.10

February 16, 2007

tor can also be connected between OSC1 and OSC2 to

get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required (If the oscillating fre-

quency is less than 1MHz).

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works with a

period of approximately 65

ms at 5V. The WDT oscillator

can be disabled by options to conserve power.

Watchdog Timer

- WDT

The clock source of WDT is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock divided by 4), decided by options. This timer is

designed to prevent a software malfunction or sequence

from jumping to an unknown location with unpredictable

results. The Watchdog Timer can be disabled by an op-

tion. If the Watchdog Timer is disabled, all the execu-

tions related to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator with a

period of 65

ms at 5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of approximately 17ms at 5V. This time-out period

may vary with temperatures, VDD and process varia-

tions. By invoking the WDT prescaler, longer time-out

periods can be realized. Writing data to WS2, WS1,

WS0 (bit 2,1,0 of the WDTS) can give different time-out

periods. If WS2, WS1, and WS0 are all equal to 1, the di-

vision ratio is up to 1:128, and the maximum time-out

period is 2.1s at 5V seconds. If the WDT oscillator is dis-

abled, the WDT clock may still come from the instruction

clock and operate in the same manner except that in the

HALT state the WDT may stop counting and lose its pro-

tecting purpose. In this situation the logic can only be re-

started by external logic. The high nibble and bit 3 of the

WDTS are reserved for user

¢s defined flags, which can

be used to indicate some specified status.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

WDTS (09H) Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a

²warm reset², and

only the Program Counter and SP are reset to zero. To

clear the contents of WDT (including the WDT

prescaler), three methods are adopted; external reset (a

low level to RES), software instruction and a

²HALT² in-

struction. The software instruction include

²CLR WDT²

and the other set

-²CLR WDT1² and ²CLR WDT2².Of

these two types of instruction, only one can be active de-

pending on the option

-²CLR WDT times selection op-

tion

².Ifthe ²CLR WDT² is selected (i.e. CLRWDT times

equal one), any execution of the

²CLR WDT² instruction

will clear the WDT. In the case that

²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLRWDT times equal

two), these two instructions must be executed to clear

the WDT; otherwise, the WDT may reset the chip as a

result of time-out.

Power Down Operation

- HALT

The HALT mode is initialized by the

²HALT² instruction

and results in the following...

· The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

· The contents of the on chip RAM and registers remain

unchanged.

· WDT will be cleared and recounted again (if the WDT

clock is from the WDT oscillator).

S y s t e m C l o c k / 4

8 - b i t C o u n t e r

W D T P r e s c a l e r

7 - b i t C o u n t e r

8 - t o - 1 M U X

W D T T i m e - o u t

W S 0 ~ W S 2

O p t i o n

S e l e c t

W D T

O S C

Watchdog Timer

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