HT45RM03 datasheet(10/54 Pages) HOLTEK

10 / 54 page

HT45RM03

Rev. 1.10

February 16, 2007

Interrupt

The devices provides four external interrupts, two inter-

nal Timer/Event Counter 0/1 interrupts, one comparator

interrupt, and PWM period interrupt. The interrupt con-

trol register 0 (INTC0;0BH) and interrupt control register

1 (INTC1;1EH) both contain the interrupt control bits

that are used to set the enable/disable status and inter-

rupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt requires servicing within the service routine, the

EMI bit and the corresponding bit of INTC0 and INTC1

may be set to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if the

related interrupt is enabled, until the SP is decremented.

If immediate service is desired, the stack must be pre-

vented from becoming full.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

The Comparator output Interrupt is initialized by setting

the Comparator output Interrupt request flag (CF; bit 4 of

the INTC0), which is caused by a falling edge transition

of comparator output. After the interrupt is enabled, and

the stack is not full, and the CF bit is set, a subroutine

call to location 04H occurs. The related interrupt request

flag (CF) is reset, and the EMI bit is cleared to disable

further maskable interrupts.

External interrupts are triggered by a an edge transition

of INT0A, INT0B, INT0C or INT1 (software control: high

to low, low to high, low to high or high to low), and the re-

lated interrupt request flag (EIF0; bit 5 of INTC0, EIF1;

bit 6 of INTC0) is set as well. After the interrupt is en-

abled, the stack is not full, and the external interrupt is

active, a subroutine call to location 08H or 0CH occurs.

The interrupt request flag (EIF0 or EIF1) and EMI bits

are all cleared to disable other maskable interrupts.

The PWM period interrupt is initialized by setting the

PWM period interrupt request flag (PWMF; bit 4 of

INTC1), that is caused by a regular PWM period signal.

After the interrupt is enabled, and the stack is not full,

and the PWMF bit is set, a subroutine call to location

10H occurs. The related interrupt request flag (PWMF)

is reset and the EMI bit is cleared to disable further

maskable interrupts.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 5 of the INTC1), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 014H occurs. The related in-

terrupt request flag (T0F) is reset, and the EMI bit is

cleared to disable further interrupts. The Timer/Event

Counter 1 is operated in the same manner, The

Timer/Event Counter 1 related interrupt request flag is

T1F (bit 6 of the INTC1) and its subroutine call location

is 018H. The related interrupt request flag (T1F) will be

reset and the EMI bit cleared to disable further inter-

rupts.

Bit No.

Label

Function

EMI

Control the master (global) interrupt (1=enabled; 0=disabled)

ECI

Control the Comparator interrupt (1=enabled; 0=disabled)

EEI0

Control the external INT0A, INT0B, INT0C interrupt(1=enabled; 0=disabled)

EEI1

Control the external INT1 interrupt (1=enabled; 0=disabled)

The Comparator request flag (1=active; 0=inactive)

EI0F

External interrupt INT0A, INT0B, INT0C request flag (1=active; 0=inactive)

EI1F

External interrupt INT1 request flag (1=active; 0=inactive)

Unused bit, read as

²0².

INTC0 (0BH) Register

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