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2-4

Viterbi Decoder Implementation

The Viterbi Algorithm

Viterbi Decoder

Error correcting codes have some standard notation. This example, used in the wireless

standard IS-136, is a rate 1/2 code, meaning that for each processing period, one

information bit is taken in and two bits of output are generated. The word (S4,S3,S2,S1,S0)

is the encoder state. The remaining bit of the encoder we call the input bit. There is a

convenient notation that describes the encoder using polynomials. This encoder can be

described with the encoding polynomials (1+D+D3+D5,1+D2+D3+D4+D5). Each factor D

corresponds to a one clock delay for that adder input. Given the encoding polynomials,

we can begin to design the Viterbi decoder.

2.3

VITERBI DECODER

To design a Viterbi decoder, begin by taking some example encoder input and

generating the corresponding output. An example appears in Table 2-1, where it is

assumed that the encoder is 0 filled at the start. For proper decoding, we need to recreate

the encoder states and find the set of state changes, or transitions, that produce an

encoder output that best agrees with our decoder input data. We begin using the same

assumption we used in generating the encoder output in Table 2-1. We assume that the

initial state of the encoder is 00000.

Table 2-1

Input/Output Mapping

To compare our recreated encoder state with the decoder input, we keep track of the

agreements between the recreated encoder outputs and the decoder inputs. The

cumulative agreement for a path leading to one particular recreated encoder state is

called a path metric for that path. Incremental agreements are called branch metrics.

Encoder

Input

Encoder

Output

111

010

110

010

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