DSP56300 datasheet(77/108 Pages) FREESCALE

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Basic Algorithm Program Listing

Viterbi Decoder Implementation

A-9

;**********************MEMORY ORGANIZATION****************************

;

MOST OF THE MEMORY LOCATION IS IMPORTANT--THE FIRST TWO

;

LABELS OF THE X AND Y DATA MEMORY ARE PAIRED AND MUST

;

BE CO LOCATED (AT THE SAME ADDRESSES).

IN ADDITION, STATE1

;

AND STATE2 MUST BE LOCATED ON A 0 MOD 2*NUMSTATES BOUNDARY,

;

X and Y memory for input data must be paired --GOOD LUCK.....

;*****************************************************************************

;*********************************************************************

;

org

x:$0

STATE1

$0ff,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0

$0,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0

STATE2

$0ff,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0

$0,$0,$0,$0,$0,$0,$0,$0,0,0,0,0,0,0,0,0

;

PATHOUT DS

NUMSTATES*(NUMINPUTS/8+1)

INDATA

;THIS DATA ENCODES

$1234,$5678,$9abc,$4973,$7925,$3491,$ad43,$ff21,$7ebb,$0100,$20

$a000,$a000,$a000,$6000,$6000,$a000,$a000,$6000

$6000,$6000,$6000,$6000,$6000,$a000,$a000,$6000

$a000,$6000,$a000,$6000,$a000,$6000,$a000,$6000

$a000,$a000,$6000,$6000,$6000,$a000,$a000,$a000

$a000,$a000,$a000,$a000,$a000,$a000,$a000,$a000

$a000,$6000,$6000,$a000,$a000,$a000,$a000,$a000

$a000,$a000,$a000,$a000,$a000,$6000,$6000,$a000

$6000,$a000,$6000,$a000,$6000,$6000,$6000,$6000

$a000,$a000,$6000,$6000,$a000,$a000,$a000,$6000

$a000,$6000,$a000,$6000,$6000,$a000,$6000,$a000

$a000,$a000,$6000,$a000,$a000,$a000,$a000,$6000

$6000,$6000,$6000,$a000,$6000,$6000,$6000,$6000

$6000,$6000,$a000,$a000,$a000,$a000,$6000,$6000

$a000,$a000,$6000,$a000,$a000,$a000,$a000,$a000

$a000,$6000,$6000,$a000,$a000,$a000,$a000,$a000

$6000,$a000,$6000,$a000,$6000,$6000,$a000,$a000

$6000,$6000,$6000,$a000,$a000,$6000,$a000,$6000

$6000,$6000,$a000,$a000,$a000,$6000,$a000,$a000

$a000,$a000,$6000,$6000,$6000,$a000,$a000,$6000

$6000,$a000,$6000,$a000,$6000,$a000,$a000,$a000

$a000,$a000,$6000,$6000,$a000,$6000,$a000,$6000

;*****************************************************************************

Example A-1

Basic 16-Bit Implementation of a Viterbi Decoder (Continued)

Freescale Semiconductor, Inc.

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