DSP56300 datasheet(17/108 Pages) FREESCALE

номер детали	DSP56300

подробное описание детали	Implementing Viterbi Decoders Using the VSL Instruction on DSP Families

PDF	108 Pages

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The Viterbi Algorithm

IS-136

Viterbi Decoder Implementation

2-3

2.1

IS-136

This section introduces the Viterbi algorithm through an example from industry: the

convolutional error correcting code used in IS-136, the TIA/EIA interim wireless

standard. Here it is shown how the algorithm is derived, and some typical

computational enhancements are introduced.

2.2

CONVOLUTIONAL ENCODING

The Viterbi algorithm can be usefully illustrated by implementing a convolutional code.

A convolutional encoder implementation in hardware is illustrated schematically in

Figure 2-1

. In order to illustrate the steps needed to implement Viterbi decoders in

general, this application report develops the assembly code needed to implement a

Viterbi algorithm decoder for this encoder.

Figure 2-1

Example Rate 1/2 Convolutional Encoder

In this figure, the square boxes represent a one-bit-wide shift register. Some shift register

outputs are connected to modulo 2 adders (i.e., parity generators). Every time one bit is

shifted into the input, two output bits are generated by the adders. Because we have

more output bits than input bits, we have redundancy. The redundant information can

be used to correct errors at the receiver.

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DSP56300 датащи(PDF) 17 Page - Freescale Semiconductor, Inc