DSP56300 datasheet(73/108 Pages) FREESCALE

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Basic Algorithm Program Listing

Viterbi Decoder Implementation

A-5

;

;*******************viterbi add, compare, select butterfly macro***

;

FUNCTION: Update path metrics/paths for the Viterbi algorithm by

;

doing an add,compare,select update for state pairs.

;

INPUTS:

;

r2 should point to the beginning of the branch metric table

;

r5 should point to the latest path metric for state 0

;

r4 should point to the storage location for updated state 0

;

n5 should offset addresses by NUMSTATES/2

;

OUTPUTS:

;

Updated path metrics/paths stored in XY memory

;

REGISTERS USED:

;

a,b,x0,y1,r2,r4,r5,n5 r2 unchanged (modulo req'd)

;

Registers:

;

r5, pointer to the path metric/path table, arranged as

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x: path metric, y: path,states ordered assuming

;

bits shift right to left.

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r4, pointer to the output path metric/path table

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r0, pointer to the branch metric table, arranged

;

as x:C, y:D, CD,CD,CD, etc.

;

SA------NSA

;

C /

;

D \

;

D /

;

SB------NSB

;

;*****************************************************************************

ACS

macro

;

move

#BRY,r2

;r2 points to branch metrics

move

y:(r2)+,y1

;get first branch metric

move

l:(r5)+n5,a

;load 1st metric/path pair

;

#NoOfAcsButt,_P_NextStage

;update each state

sub

y1,a

l:(r5)-n5,b

;sub pt,br met,get next pair

add

y1,b

;update metrics

max

a,b

l:(r5)+n5,a

;pick max,reload 1st pair

vsl

b,0,l:(r4)+

;store survivor,end top half

add

y1,a

l:(r5)-n5,b

;add pt,br met,reload next pair

sub

y1,b

x:(r5)+,x0

y:(r2)+,y1

;inc st ptr,ld nxt br met

max

a,b

l:(r5)+n5,a

;pick max met,load next pair

vsl

b,1,l:(r4)+

;st survivor,end 2nd half

_P_NextStage

nop

;needed to separate do loop ends

endm

Example A-1

Basic 16-Bit Implementation of a Viterbi Decoder (Continued)

Freescale Semiconductor, Inc.

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