PM7344 datasheet(91/293 Pages) PMC

91 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

RDLINTE:

The RDLINTE bit enables the RFDL received-data interrupt to also generate

an interrupt on the microprocessor interrupt, INTB. This allows a single

microprocessor to service the RFDL without needing to interface to the DMA

control signals. When RDLINTE is set to logic 1, an event causing an

interrupt in the RFDL (which is visible on the RDLINT[x] output pin when

RXDMASIG is logic 1) also causes an interrupt to be generated on the INTB

output. When RDLINTE is set to logic 0, an interrupt event in the RFDL does

not cause an interrupt on INTB.

RDLEOME:

The RDLEOME bit enables the RFDL end-of-message interrupt to also

generate an interrupt on the microprocessor interrupt, INTB. This allows a

single microprocessor to service the RFDL without needing to interface to the

DMA control signals. When RDLEOME is set to logic 1, an end-of-message

event causing an EOM interrupt in the RFDL (which is visible on the

RDLEOM[x] output pin when RXDMASIG is logic 1) also causes an interrupt

to be generated on the INTB output. When RDLEOME is set to logic 0, an

EOM interrupt event in the RFDL does not cause an interrupt on INTB.

NOTE: within the RFDL, an end-of-message event causes an interrupt on

both the EOM and INT RFDL interrupt outputs. See the Operation section for

further details on using the RFDL.

TDLINTE:

The TDLINTE bit enables the XFDL request for service interrupt to also

generate an interrupt on the microprocessor interrupt, INTB. This allows a

single microprocessor to service the XFDL without needing to interface to the

DMA control signals. When TDLINTE is set to logic 1, an request for service

interrupt event in the XFDL (which is visible on the TDLINT[x] output pin

when TXDMASIG is logic 1) also causes an interrupt to be generated on the

INTB output. When TDLINTE is set to logic 0, an interrupt event in the XFDL

does not cause an interrupt on INTB.

TDLUDRE:

The TDLUDRE bit enables the XFDL transmit data underrun interrupt to also

generate an interrupt on the microprocessor interrupt, INTB. This allows a

single microprocessor to service the XFDL without needing to interface to the

DMA control signals. When TDLUDRE is set to logic 1, an underrun event

causing an interrupt in the XFDL (which is visible on the TDLUDR[x] output

pin when TXDMASIG is logic 1) also causes an interrupt to be generated on

the INTB output. When TDLUDRE is set to logic 0, an underrun event in the

XFDL does not cause an interrupt on INTB.

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