PM7344 datasheet(90/293 Pages) PMC

90 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Registers 002H, 102H, 202H and 302H: Datalink Options

Bit

Type

Function

Default

Bit 7

R/W

RXDMASIG

Bit 6

Unused

Bit 5

R/W

TXDMASIG

Bit 4

Unused

Bit 3

R/W

RDLINTE

Bit 2

R/W

RDLEOME

Bit 1

R/W

TDLINTE

Bit 0

R/W

TDLUDRE

These registers allow software to configure the datalink options of each T1 or E1

interface.

RXDMASIG:

The RXDMASIG bit selects the internal HDLC receiver (RFDL) data-received

interrupt (INT) and end-of-message (EOM) signals to be output on the

RDLINT[x] and RDLEOM[x] pins. When RXDMASIG is set to logic 1, the

RDLINT[x] and RDLEOM[x] output pins can be used by a DMA controller to

process the datalink. When RXDMASIG is set to logic 0, the RFDL INT and

EOM signals are no longer available to a DMA controller; the signals on

RDLINT[x] and RDLEOM[x] become the extracted datalink data and clock,

RDLSIG[x] and RDLCLK[x]. In this mode, the data stream available on the

RDLSIG[x] output corresponds to the extracted facility datalink for T1-ESF, or

to the extracted timeslot 0 National bits or timeslot 16 for E1.

TXDMASIG:

The TXDMASIG bit selects the internal HDLC transmitter (XFDL) request for

service interrupt (INT) and data underrun (UDR) signals to be output on the

TDLINT[x] and TDLUDR[x] pins. When TXDMASIG is set to logic 1, the

TDLINT[x] and TDLUDR[x] output pins can be used by a DMA controller to

service the datalink. When TXDMASIG is set to logic 0, the XFDL INT and

UDR signals are no longer available to a DMA controller; the signals on

TDLINT[x] and TDLUDR[x] become the serial datalink data input and clock,

TDLSIG[x] and TDLCLK[x]. In this mode an external controller is responsible

for formatting the data stream presented on the TDLSIG[x] input to

correspond to the facility datalink in T1-ESF, or to the extracted timeslot 0

National bits or timeslot 16 for E1.

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