PM7344 datasheet(62/293 Pages) PMC

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PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

error events with saturating counters over consecutive intervals as defined by the

period of the supplied transfer clock signal (typically 1 second).

When the transfer clock signal is applied, the PMON transfers the counter values

into holding registers and resets the counters to begin accumulating events for

the interval. The counters are reset in such a manner that error events occurring

during the reset are not missed.

Generation of the transfer clock within the S/UNI-MPH is performed by writing to

any counter register location. The holding register addresses are contiguous to

facilitate polling operations.

9.7

T1 Bit Oriented Code Detector (RBOC)

The Bit Oriented Code detection function is provided by the RBOC block. This

block detects the presence of 63 of the possible 64 bit oriented codes

transmitted in the facility data link channel in T1-ESF framing format, as defined

in ANSI T1.403 and in TR-TSY-000194.

Bit oriented codes are received on the facility data link channel as a 16-bit

sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero

(111111110xxxxxx0) which is repeated at least 10 times. The RBOC can be

enabled to declare a received code valid if it has been observed for 8 out of 10

times or for 4 out of 5 times.

Valid BOCs are indicated through an internal status register. The BOC bits are

set to all ones (111111) if no valid code has been detected. An interrupt is

generated to signal when a detected code has been validated, or optionally,

when a valid code is removed (i.e. the BOC bits go to all ones idle state).

9.8

HDLC Receiver (RFDL)

The HDLC Receiver function is provided by the RFDL block. The RFDL is a

microprocessor peripheral used to receive LAPD/HDLC frames on the ESF

facility data link (FDL) for T1 interfaces, or on timeslot 16 or the National use bits

of timeslot 0 for E1 interfaces.

The RFDL detects the change from flag characters to the first byte of data,

removes stuffed zeros on the incoming data stream, receives frame data, and

calculates the CRC-CCITT frame check sequence (FCS).

Received data is placed into a 4-level FIFO buffer. The Status Register contains

bits which indicate overrun, end of message, flag detected, and buffered data

available.

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