PM7344 datasheet(61/293 Pages) PMC

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PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

condition has been absent for 16.6 sec (± 500 ms). The presence of AIS CFA is

declared when an out-of-frame condition and all-ones in the data stream have

been present for 1.5 sec (±100 ms); the AIS CFA is removed when the AIS

condition has been absent for 16.8 sec (±500 ms).

For E1 formats, the ALMI block declares the presence of red CFA when an out-

of-frame condition has been present for 104 ms (±6 ms); the red CFA is removed

when the out-of-frame condition has been absent for 104 ms (±6 ms). The

presence of AIS CFA is declared when an out-of-frame condition and all-ones in

the data stream have been present for 104 ms (±6 ms); the AIS CFA is removed

when the AIS condition has been absent for 104 ms (±6 ms).

CFA alarm detection algorithms operate in the presence of a random 10-3 bit

error rate.

The ALMI also indicates the presence or absence of the T1 yellow, red, and AIS

alarm signal conditions over 40 ms, 40ms, and 60 ms intervals, respectively,

allowing an external microprocessor to integrate the alarm conditions via

software with any user-specific algorithms. Alarm indication is provided through

internal register bits.

9.5

T1 Inband Loopback Code Detector (IBCD)

The T1 Inband Loopback Code Detection function is provided by the IBCD block.

This block detects the presence of either of two programmable loopback code

sequences, ACTIVATE and DEACTIVATE, in either framed or unframed T1 data

streams. The inband code sequences are expected to be overwritten by the

framing bit in framed data streams. Each code sequence is defined as the

repetition of the programmed code in the PCM stream for at least 5.1 seconds.

The code sequence detection and timing is compatible with the specifications

defined in T1.403, TA-TSY-000312, and TR-TSY-000303. ACTIVATE and

DEACTIVATE code indication is provided through internal register bits. An

interrupt is generated to indicate when either code status has changed.

9.6

Performance Monitor Counters (PMON)

The Performance Monitor Counters function is provided by the PMON block. For

a T1 data stream, the PMON accumulates CRC-6 error events, frame

synchronization bit error events, line code violation events, and loss of frame

events, or optionally, change of frame alignment (COFA) events with saturating

counters over consecutive intervals as defined by the period of the supplied

transfer clock signal (typically 1 second).

For an E1 data stream, the PMON accumulates CRC-4 error events, frame

synchronization bit error events, line code violation events, and far end block

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