PM7344 datasheet(40/293 Pages) PMC

40 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

Pin Name

Type

No.

Function

TFPI

Input

106

Transmit Frame Position (TFPI). This signal

provides the transmit frame position indication

for the four T1/E1 framers. TFPI can be used in

applications where the transmit frames must be

aligned to a common reference. In these

applications, TFPI is activated for one clock

period every 193 (T1) or 256 (E1) TCLKI periods

(or multiple thereof). If such alignment is not

required, TFPI may be tied low. TFPI may be

configured to be active high or active low, and

may be enabled to be sampled on the rising or

falling edge of TCLKI.

TOHI

Transmit Overhead Mask Input (TOHI). This

signal identifies the placeholder bits in the

transmit stream for arbitrary bit rate interfaces.

A delayed version of TOHI appears on the four

TOHO outputs. Downstream framing insertion

devices overwrite the placeholder bit positions

with overhead specific to a particular frame

format (for example the 6.312 Mbit/s J2 format).

TOHI may be configured to be active high or

active low, and may be enabled to be sampled

on the rising or falling edge of TCLKI.

XCLK/

Input

108

Crystal Clock Input (XCLK). This signal

provides timing for the T1 or E1 framer portion

of the S/UNI-MPH. Depending on the

configuration of the S/UNI-MPH, XCLK must be

nominally 24x or 8x the nominal line rate. The

8x clock is used by the clock recovery digital

phase locked loop and the T1/E1 framer, while

the 24x clock is used by the jitter attenuator in

the S/UNI-MPH. This clock may be tied low if

the T1/E1 framers are bypassed. The default

requirement is for XCLK to be a 37.056 MHz

clock for T1 or a 49.152 MHz clock for E1.

VCLK

Vector Clock (VCLK). The VCLK signal is used

during S/UNI-MPH production test to verify

internal functionality.

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