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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADAU1361BCPZ-R7 датащи(PDF) 23 Page - Analog Devices |
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ADAU1361BCPZ-R7 датащи(HTML) 23 Page - Analog Devices |
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23 / 78 page  Data Sheet ADAU1361 STARTUP, INITIALIZATION, AND POWER analog.com Rev. E | 23 of 78 PLL Lock Acquisition During the lock acquisition period, only Register R0 (Address 0x4000) and Register R1 (Address 0x4002) are accessible through the control port. Because all other registers require a valid main clock for reading and writing, do not attempt to access any other register. Any read or write is prohibited until the core clock enable bit (COREN) and the lock bit are both asserted. To program the PLL during initialization or reconfiguration of the clock setting, the following procedure must be followed: 1. Power down the PLL. 2. Reset the PLL control register. 3. Start the PLL. 4. Poll the lock bit. 5. Assert the core clock enable bit after the PLL lock is acquired. The PLL control register (Register R1, Address 0x4002) is a 48-bit register where all bits must be written with a single continuous write to the control port. |
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