ADAU1361BCPZ-R7 datasheet(31/78 Pages) AD

31 / 78 page

Data Sheet

ADAU1361

AUTOMATIC LEVEL CONTROL (ALC)

analog.com

Rev. E | 31 of 78

Figure 38. Effect of Varying the Maximum Gain Parameter

NOISE GATE FUNCTION

When using the ALC, one potential problem is that for small input

signals, the PGA gain can become very large. A side effect of this

is that the noise is amplified along with the signal of interest. To

avoid this situation, the ADAU1361 noise gate can be used. The

noise gate cuts off the ADC output when its signal level is below

a set threshold. The noise gate is controlled using the following

parameters in the ALC Control 3 register (Address 0x4014):

►

NGTYP[1:0]: The noise gate type is set to one of four modes by

writing to the NGTYP[1:0] bits.

►

NGEN: The noise gate function is enabled by writing to the

NGEN bit.

►

NGTHR[4:0]: The threshold for muting the output is set by writing

to the NGTHR[4:0] bits.

One common problem with noise gate functions is chatter, where

a small signal that is close to the noise gate threshold varies

in amplitude, causing the noise gate function to open and close

rapidly. This causes an unpleasant sound.

To reduce this effect, the noise gate in the ADAU1361 uses a

combination of a timeout period and hysteresis. The timeout period

is set to 250 ms, so the signal must consistently be below the

threshold for 250 ms before the noise gate operates. Hysteresis is

used so that the threshold for coming out of the mute state is 6 dB

higher than the threshold for going into the mute state. There are

four operating modes for the noise gate.

Noise Gate Mode 0 (see Figure 39) is selected by setting the

NGTYP[1:0] bits to 00. In this mode, the current state of the

PGA gain is held at its current state when the noise gate logic

is activated. This prevents a large increase in background noise

during periods of silence. When using this mode, it is advisable to

use a relatively slow decay time. This is because the noise gate

takes at least 250 ms to activate, and if the PGA gain has already

increased to a large value during this time, the value at which the

gain is held is large.

Figure 39. Noise Gate Mode 0 (PGA Gain Hold)

Noise Gate Mode 1 (see Figure 40) is selected by setting the

NGTYP[1:0] bits to 01. In this mode, the ADAU1361 does a simple

digital mute of the ADC output. Although this mode completely

eliminates any background noise, the effect of an abrupt mute may

not be pleasant to the ear.

Figure 40. Noise Gate Mode 1 (Digital Mute)

Noise Gate Mode 2 (see Figure 41) is selected by setting the

NGTYP[1:0] bits to 10. In this mode, the ADAU1361 improves the

sound of the noise gate operation by first fading the PGA gain over

a period of about 100 ms to the minimum PGA gain value. The

ADAU1361 does not do a hard mute after the fade is complete, so

some small background noise still exists.

ADAU1361BCPZ-R7 датащи(PDF) 31 Page - Analog Devices

ADAU1361BCPZ-R7 датащи(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL