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ADAU1361BCPZ-R7 датащи(PDF) 25 Page - Analog Devices

номер детали ADAU1361BCPZ-R7
подробное описание детали  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  78 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADAU1361BCPZ-R7 датащи(HTML) 25 Page - Analog Devices

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Data Sheet
ADAU1361
CLOCKING AND SAMPLING RATES
analog.com
Rev. E | 25 of 78
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
Common fractional PLL parameter settings for 44.1 kHz and 48 kHz
sampling rates can be found in Table 16 and Table 17.
The PLL outputs a clock in the range of 41 MHz to 54 MHz, which
should be taken into account when calculating PLL values and
MCLK frequencies.
Table 15. PLL Control Register (Register R1, Address 0x4002)
Bits
Bit Name
Description
[47:32]
M[15:0]
Denominator of the fractional PLL: 16-bit binary number
0x00FD: M = 253 (default)
[31:16]
N[15:0]
Numerator of the fractional PLL: 16-bit binary number
0x000C: N = 12 (default)
[14:11]
R[3:0]
Integer part of PLL: four bits, only values 2 to 8 are valid
0010: R = 2 (default)
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 71000: R = 8
[10:9]
X[1:0]
PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
8
Type
PLL operation mode
0: Integer (default)
1: Fractional
1
Lock
PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
0
PLLEN
PLL enable
0: PLL disabled (default)
1: PLL enabled
Table 16. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)
8
1
5
625
403
0x0271 0193 2901
12
1
3
625
477
0x0271 01DD 1901
13
1
3
8125
3849
0x1FBD 0F09 1901
14.4
2
6
125
34
0x007D 0022 3301
19.2
2
4
125
88
0x007D 0058 2301
19.68
2
4
1025
604
0x0401 025C 2301
19.8
2
4
1375
772
0x055F 0304 2301
24
2
3
625
477
0x0271 01DD 1B01
26
2
3
8125
3849
0x1FBD 0F09 1B01
27
2
3
1875
647
0x0753 0287 1B01
Table 17. Fractional PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)
8
1
6
125
18
0x007D 0012 3101
12
1
4
125
12
0x007D 000C 2101
13
1
3
1625
1269
0x0659 04F5 1901
14.4
2
6
75
62
0x004B 003E 3301



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