ADAU1361BCPZ-R7 datasheet(42/78 Pages) AD

42 / 78 page

Data Sheet

ADAU1361

APPLICATIONS INFORMATION

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Rev. E | 42 of 78

POWER SUPPLY BYPASS CAPACITORS

Each analog and digital power supply pin should be bypassed to

its nearest appropriate ground pin with a single 100 nF capaci-tor.

The connections to each side of the capacitor should be as short as

possible, and the trace should stay on a single layer with no vias.

For maximum effectiveness, locate the capacitor equi-distant from

the power and ground pins or, when equidistant placement is not

possible, slightly closer to the power pin. Thermal connections to

the ground planes should be made on the far side of the capacitor.

Each supply signal on the board should also be bypassed with a

single bulk capacitor (10 μF to 47 μF).

Figure 62. Recommended Power Supply Bypass Capacitor Layout

GSM NOISE FILTER

In mobile phone applications, excessive 217 Hz GSM noise on the

analog supply pins can degrade the audio quality. To avoid this

problem, it is recommended that an L-C filter be used in series with

the bypass capacitors for the AVDD pins. This filter should consist

of a 1.2 nH inductor and a 9.1 pF capacitor in series between AVDD

and ground, as shown in Figure 63.

Figure 63. GSM Filter on the Analog Supply Pins

GROUNDING

A single ground plane should be used in the application layout.

Components in an analog signal path should be placed away from

digital signals.

EXPOSED PAD PCB DESIGN

The ADAU1361 has an exposed pad on the underside of the

LFCSP. This pad is used to couple the package to the PCB for heat

dissipation when using the outputs to drive earpiece or headphone

loads. When designing a board for the ADAU1361, special consid-

eration should be given to the following:

►

A copper layer equal in size to the exposed pad should be on

all layers of the board, from top to bottom, and should connect

somewhere to a dedicated copper board layer (see Figure 64).

►

Vias should be placed to connect all layers of copper, allowing

for efficient heat and energy conductivity. For an example, see

Figure 65, which has nine vias arranged in a 3 inch × 3 inch grid

in the pad area.

Figure 64. Exposed Pad Layout Example, Side View

Figure 65. Exposed Pad Layout Example, Top View

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