ADAU1361BCPZ-R7 datasheet(24/78 Pages) AD

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Data Sheet

ADAU1361

CLOCKING AND SAMPLING RATES

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Rev. E | 24 of 78

Figure 29. Clock Tree Diagram

CORE CLOCK

Clocks for the converters and serial ports are derived from the core

clock. The core clock can be derived directly from MCLK or it can

be generated by the PLL. The CLKSRC bit (Bit 3 in Register R0,

Address 0x4000) determines the clock source.

The INFREQ[1:0] bits should be set according to the expected input

clock rate selected by CLKSRC; this value also determines the core

clock rate and the base sampling frequency, fS.

For example, if the input to CLKSRC = 49.152 MHz (from PLL),

then

INFREQ[1:0] = 1024 × fS

fS = 49.152 MHz/1024 = 48 kHz

The PLL output clock rate is always 1024 × fS, and the clock

control register automatically sets the INFREQ[1:0] bits to 1024 ×

fS when using the PLL. When using a direct clock, the INFREQ[1:0]

frequency should be set according to the MCLK pin clock rate and

the desired base sampling frequency.

Table 12. Clock Control Register (Register R0, Address 0x4000)

Bits

Bit Name

Settings

CLKSRC

0: Direct from MCLK pin (default) 1: PLL clock

[2:1]

INFREQ[1:0]

00: 256 × fS (default)01: 512 × fS10: 768 × fS11:

1024 × fS

COREN

0: Core clock disabled (default)1: Core clock

enabled

SAMPLING RATES

The ADCs, DACs, and serial port share a common sampling rate

that is set in Register R17 (Converter Control 0 register, Address

0x4017). The CONVSR[2:0] bits set the sampling rate as a ratio of

the base sampling frequency.

Table 13 and Table 14 list the sampling rate divisions for common

base sampling rates.

Table 13. 48 kHz Base Sampling Rate Divisions

Base Sampling

Frequency

Sampling Rate Scaling

Sampling Rate

fS = 48 kHz

fS/1

48 kHz

fS/6

8 kHz

fS/4

12 kHz

fS/3

16 kHz

fS/2

24 kHz

Table 13. 48 kHz Base Sampling Rate Divisions (Continued)

Base Sampling

Frequency

Sampling Rate Scaling

Sampling Rate

fS/1.5

32 kHz

fS/0.5

96 kHz

Table 14. 44.1 kHz Base Sampling Rate Divisions

Base Sampling

Frequency

Sampling Rate Scaling

Sampling Rate

fS = 44.1 kHz

fS/1

44.1 kHz

fS/6

7.35 kHz

fS/4

11.025 kHz

fS/3

14.7 kHz

fS/2

22.05 kHz

fS/1.5

29.4 kHz

fS/0.5

88.2 kHz

PLL

The PLL uses the MCLK as a reference to generate the core clock.

PLL settings are set in Register R1 (PLL control register, Address

0x4002). Depending on the MCLK frequency, the PLL must be set

for either integer or fractional mode. The PLL can accept input

frequencies in the range of 8 MHz to 27 MHz.

All six bytes in the PLL control register must be written with a single

continuous write to the control port.

Figure 30. PLL Block Diagram

Integer Mode

Integer mode is used when the MCLK is an integer (R) multiple of

the PLL output (1024 × fS).

For example, if MCLK = 12.288 MHz and fS = 48 kHz, then

PLL required output = 1024 × 48 kHz = 49.152 MHz

R = 49.152 MHz/12.288 MHz = 4

In integer mode, the values set for N and M are ignored.

Fractional Mode

Fractional mode is used when the MCLK is a fractional (R + (N/M))

multiple of the PLL output.

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