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ADAU1361BCPZ-R7 датащи(PDF) 10 Page - Analog Devices

номер детали ADAU1361BCPZ-R7
подробное описание детали  Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL
PDF  78 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADAU1361BCPZ-R7 датащи(HTML) 10 Page - Analog Devices

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Data Sheet
ADAU1361
SPECIFICATIONS
analog.com
Rev. E | 10 of 78
Table 7. Digital Timing (Continued)
Parameter
Limit
Unit
Description
tMIN
tMAX
tCCPH
10
ns
CCLK pulse width high.
tCLS
5
ns
CLATCH setup. Time to CCLK rising.
tCLH
10
ns
CLATCH hold. Time from CCLK rising.
tCLPH
10
ns
CLATCH pulse width high.
tCDS
5
ns
CDATA setup. Time to CCLK rising.
tCDH
5
ns
CDATA hold. Time from CCLK rising.
tCOD
50
ns
COUT three-stated. Time from CLATCH rising.
I2C PORT
fSCL
400
kHz
SCL frequency.
tSCLH
0.6
µs
SCL high.
tSCLL
1.3
µs
SCL low.
tSCS
0.6
µs
Setup time; relevant for repeated start condition.
tSCH
0.6
µs
Hold time. After this period, the first clock is generated.
tDS
100
ns
Data setup time.
tSCR
300
ns
SCL rise time.
tSCF
300
ns
SCL fall time.
tSDR
300
ns
SDA rise time.
tSDF
300
ns
SDA fall time.
tBFT
0.6
µs
Bus-free time. Time between stop and start.
DIGITAL MICROPHONE
RLOAD = 1 MΩ, CLOAD = 14 pF.
tDCF
10
ns
Digital microphone clock fall time.
tDCR
10
ns
Digital microphone clock rise time.
tDDV
22
30
ns
Digital microphone delay time for valid data.
tDDH
0
12
ns
Digital microphone delay time for data three-stated.
DIGITAL TIMING DIAGRAMS
Figure 2. Serial Input Port Timing



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