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ADAU1361BCPZ-R7 датащи(PDF) 54 Page - Analog Devices |
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ADAU1361BCPZ-R7 датащи(HTML) 54 Page - Analog Devices |
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54 / 78 page ![]() Data Sheet ADAU1361 CONTROL REGISTERS analog.com Rev. E | 54 of 78 R15: Serial Port Control 0, 16,405 (0x4015) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DITHEN Reserved LRMOD BPOL LRPOL CHPF[1:0] MS Table 42. Serial Port Control 0 Register Bits Bit Name Description 7 DITHEN Dither enable is applicable only for 16-bit data width modes. 0 = disabled (default). 1 = enabled. 5 LRMOD LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide. 0 = 50% duty cycle (default). 1 = pulse mode. 4 BPOL BCLK polarity sets the BCLK edge that triggers a change in audio data. This can be set for the falling or rising edge of the BCLK. 0 = falling edge (default). 1 = rising edge. 3 LRPOL LRCLK polarity sets the LRCLK edge that triggers the beginning of the left channel audio frame. This can be set for the falling or rising edge of the LRCLK. 0 = falling edge (default). 1 = rising edge. [2:1] CHPF[1:0] Channels per frame sets the number of channels per LRCLK frame. Setting Channels per LRCLK Frame 00 Stereo (default) 01 TDM 4 10 Reserved 11 Reserved 0 MS Serial data port bus mode. Both LRCLK and BCLK are main of the serial port when set in main mode and are serial port subordinate in subordinate mode. 0 = subordinate mode (default). 1 = main mode. R16: Serial Port Control 1, 16,406 (0x4016) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BPF[2:0] ADTDM DATDM MSBP LRDEL[1:0] Table 43. Serial Port Control 1 Register Bits Bit Name Description [7:5] BPF[2:0] Number of bit clock cycles per LRCLK audio frame. Setting Bit Clock Cycles 000 64 (default) 001 32 010 48 011 128 100 Reserved 101 Reserved 110 Reserved 111 Reserved 4 ADTDM ADC serial audio data channel position in TDM mode. 0 = left first (default). 1 = right first. 3 DATDM DAC serial audio data channel position in TDM mode. |
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