ADAU1361BCPZ-R7 datasheet(51/78 Pages) AD

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Data Sheet

ADAU1361

CONTROL REGISTERS

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Rev. E | 51 of 78

Table 38. ALC Control 0 Register (Continued)

Bits

Bit Name

Description

96 ms

Off

[5:3]

ALCMAX[2:0]

The maximum ALC gain sets a limit to the amount of gain that the ALC can provide to the input signal. This protects small signals from

excessive amplification.

Setting

Maximum ALC Gain

000

−12 dB (default)

001

−6 dB

010

0 dB

011

6 dB

100

12 dB

101

18 dB

110

24 dB

111

30 dB

[2:0]

ALCSEL[2:0]

ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds only to the right channel

input and controls the gain of the right PGA amplifier only. When set to left only, the ALC responds only to the left channel input and controls

the gain of the left PGA amplifier only. When set to stereo, the ALC responds to the greater of the left or right channel and controls the gain

of both the left and right PGA amplifiers. These bits must be off if manual control of the volume is desired.

Setting

Channels

000

Off (default)

001

Right only

010

Left only

011

Stereo

100

Reserved

101

Reserved

110

Reserved

111

Reserved

R12: ALC Control 1, 16,402 (0x4012)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ALCHOLD[3:0]

ALCTARG[3:0]

Table 39. ALC Control 1 Register

Bits

Bit Name

Description

[7:4]

ALCHOLD[3:0]

ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before increasing the gain to

achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent distortion of low frequency signals. The hold time

doubles with every 1-bit increase.

Setting

Hold Time

0000

2.67 ms (default)

0001

5.34 ms

0010

10.68 ms

0011

21.36 ms

0100

42.72 ms

0101

85.44 ms

0110

170.88 ms

0111

341.76 ms

1000

683.52 ms

1001

1.367 sec

1010

2.7341 sec

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