RT600 datasheet(77/171 Pages) NXP

77 / 171 page

RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

77 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

– 8 flexible and configurable buffers in AHB RX Buffer

– AHB TX Buffer implemented to buffer all write data from one AHB burst. AHB TX

Buffer size: 8 * 64 Bits

– All AHB masters share this AHB TX Buffer. No AHB master number limitation for

Write Access.

• Software triggered Flash read/write access by IP Bus

– IP RX FIFO implemented to buffer all read data from External device. FIFO size:

64 * 64 Bits

– IP TX FIFO implemented to buffer all Write data to External device. FIFO size: 128

* 64 Bits

– DMA support to fill IP TX FIFO

– DMA support to read IP RX FIFO

– SCLK stopped when reading flash data and IP RX FIFO is full

– SCLK stopped when writing flash data and IP TX FIFO is empty

10.17.3 SD/eMMC Interfaces

SD/eMMC memory card interface is available with dedicated DMA controller. Supports the

eMMC 5.0 standard including HS400 DDR mode. HS-400 is supported on SD port 0 only.

10.17.4 Flexcomm Interface serial communication

10.17.4.1 Features

• USART with asynchronous operation or synchronous master or slave operation.

• SPI master or slave, with up to 4 slave selects.

• I2C, including separate master, slave, and monitor functions.

• Two I2S functions using Flexcomm Interface 6 and Flexcomm Interface 7.

• Data for USART, SPI, and I2S traffic uses the Flexcomm Interface FIFO. The I2C

function does not use the FIFO.

10.17.4.2 SPI serial I/O controller (Flexcomm Interfaces 0 - 7)

Features

• Excluding delays introduced by external device and PCB, The maximum supported bit

rate for SPI master mode (transmit/receive) is 25 Mbit/s and the maximum supported

bit rate for SPI slave mode (transmit/receive) is 25 Mbit/s.

• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or

DMA set-up.

• Master and slave operation.

• Data can be transmitted to a slave without the need to read incoming data. This can

be useful while setting up an SPI memory.

• Control information can optionally be written along with data. This allows very

versatile operation, including “any length” frames.

• Four Slave Select input/outputs with selectable polarity and flexible usage.

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