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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RT600 датащи(PDF) 68 Page - NXP Semiconductors |
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RT600 датащи(HTML) 68 Page - NXP Semiconductors |
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68 / 171 page  RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 68 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs 10.13.4 Clock Generation Fig 6. RT600 clock generation 191212 Primary clock sources (oscillators): System clocking (PLLs, CPU clocks, etc.): (1) 11 01 10 00 11 01 10 00 16m_irc Main clock select B MAINCLKSELB[1:0] (1) main_pll_clk 32k_clk clk_in Main clock select A MAINCLKSELA[1:0] 48/60m_irc_div4 1m_lposc 48/60m_irc main_clk 16 MHz oscillator 16m_irc PDRUNCFG0[15], PDSLEEPCFG0[15] xtalout Enable & bypass SYSOSCCTL0[1:0] xtalin Main crystal oscillator clk_in 0 1 clkin (selected by IOCON) SYSOSCBYPASS[2:0] rtcxout Enable OSC32KHZCTL0[0] rtcxin RTC crystal oscillator 32k_clk MCLK Clock Select AUDIOMCLKSEL[2:0] AUDIOMCLKDIV MCLK Divider to MCLK pin (output) audio_pll_clk 48/60m_irc "none" 001 111 000 48/60 MHz oscillator Divide by 2 Divide by 2 48/60m_irc 48/60m_irc_div2 48/60m_irc_div4 PDRUNCFG0[16], PDSLEEPCFG0[16] Audio PLL Divider clk_in Audio PLL clock select AUDIOPLL0CLKSEL[2:0] 16m_irc 48/60m_irc_div2 audio_pll_clk Audio PLL settings AUDIOPLL0xx PFD0 PFD1 PFD2 PFD3 Audio PLL PFD0 111 001 010 000 "none" AUDIOPLLCLKDIV (1) : synchronized multiplexer, see register descriptions for details. 1m_lposc divide by 32 WAKECLK32KHZSEL[2:0] lp_32k "none" 32k_clk 32k_wake_clk to SDIO 32k, USB 32k, ACMP sclk & rclk 1 MHz low power osc. 001 111 000 PDRUNCFG0[14], PDSLEEPCFG0[14] clk_in Sys PLL clock select SYSPLL0CLKSEL[2:0] 16m_irc 48/60m_irc_div2 Main PLL PFD0 PFD1 PFD2 PFD3 Main PLL settings SYSPLL0xx 111 001 010 000 "none" MAINPLLCLKDIV DSPPLLCLKDIV AUX1PLLCLKDIV Main PLL Clock Divider DSP PLL Clock Divider AUX1 PLL Clock Divider AUX0PLLCLKDIV AUX0 PLL Clock Divider main_pll_clk dsp_pll_clk aux1_pll_clk aux0_pll_clk 11 01 10 00 11 01 10 00 DSP clock select B DSPCPUCLKSELB[1:0] DSP clock select A DSPCPUCLKSELA[1:0] DSP Clock Divider main_pll_clk (1) dsp_pll_clk 32k_clk clk_in (1) 1m_lposc 16m_irc 48/60m_irc DSPCPUCLKDIV dsp_main_clk (to CLKOUT 0 select) to DSP CPU DSP RAM Clock Divider DSPMAINRAMCLKDIV to DSP RAM interface 011 001 010 000 111 SYSCPUAHBCLKDIV CPU Clock Divider to CPU, AHB, APB, etc. hclk SYSTICKFCLKSEL[2:0] 1m_lposc 32k_clk 16m_irc ARM Trace Clock Divider to ARM Trace function clock PFC0DIV Systick Clock Divider SYSTICKFCLKDIV to Systick function clock "none" |
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