RT600 datasheet(67/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

67 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

10.13.1.3 1 MHz Low-Power oscillator

The 1 MHz oscillator provides an ultra low-power, low-frequency clock source that can be

used to clock a variety of functions including the Watchdog Timer (WWDT) and the

OSTimer. It can also be used as the main system clock for low-power operation.

The 1 MHz Low Power oscillator is accurate to +/-10% over temperature.

10.13.1.4 Crystal oscillator

The main crystal oscillator on the RT600 can be used with crystal frequencies from 4 MHz

to 32 MHz. The crystal oscillator may be used to drive a PLL to achieve higher clock rates.

However, the practical range of crystal frequencies for PLL usage is 5 MHz to 26 MHz.

One aspect of the oscillator high gain mode is that a larger voltage swing is used at the

crystal pin. This gives a higher noise immunity within the oscillator and less edge to edge

jitter of the internal clock. When high gain mode is not required, power used by the crystal

oscillator can be reduced by using low power mode.

Remark: High gain mode requires a 1 megohm resistor to be inserted in parallel with the

crystal. See Section 16.5. For this reason, high gain mode and low power mode cannot

both be used in the same application. The board design must reflect the mode that will be

used.

10.13.1.5 32 kHz oscillator

The 32KHz oscillator resides in the “always-on” domain and is used to drive the Real Time

Clock. It is also available for use for a variety of other purposes including low-power UART

operation or as the main system clock for very low frequency operation.

10.13.2 System PLL (PLL0)

The system PLL accepts an input clock frequency in the range of 32.768 kHz to 25 MHz.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO). PLL lock time is approximately 150 us.

The PLL can be enabled or disabled by software.

10.13.3 Audio PLL (PLL2)

The audio PLL accepts an input clock frequency in the range of 1 MHz to 25 MHz. The

input frequency is multiplied up to a high frequency with a Current Controlled Oscillator

(CCO).

The PLL can be enabled or disabled by software.

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