RT600 datasheet(53/171 Pages) NXP

53 / 171 page

RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

53 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

10.5 Memory Protection Unit (MPU)

The Cortex-M33 processor has a memory protection unit (MPU) that provides fine grain

memory control, enabling applications to implement security privilege levels, separating

code, data and stack on a task-by-task basis. Such requirements are critical in many

embedded applications.

The MPU allows separating processing tasks by disallowing access to each other's data,

disabling access to memory regions, allowing memory regions to be defined as read-only

and detecting unexpected memory accesses that could potentially break the system.

The MPU separates the memory into distinct regions and implements protection by

preventing disallowed accesses. The MPU supports up to eight regions each of which can

be divided into eight subregions. Accesses to memory locations that are not defined in the

MPU regions, or not permitted by the region setting, will cause the Memory Management

Fault exception to take place.

10.6 Nested Vectored Interrupt Controller (NVIC) for Cortex-M33

The NVIC is an integral part of the Cortex-M33. The tight coupling to the CPU allows for

low interrupt latency and efficient processing of late arriving interrupts.

10.6.1 Features

• Controls system exceptions and peripheral interrupts.

• Supports up to 58 vectored interrupts.

• Eight programmable interrupt priority levels, with hardware priority level masking.

• Relocatable vector table.

• Non-Maskable Interrupt (NMI).

• Software interrupt generation.

10.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags.

10.7 System Tick timer (SysTick)

The Arm Cortex-M33 includes a system tick timer (SysTick) that is intended to generate a

dedicated SYSTICK exception. The clock source for the SysTick can be the FRO or the

Cortex-M33 core clock.

10.8 PowerQuad Hardware Accelerator

The RT600 has a PowerQuad hardware accelerator for CMSIS DSP functions (fixed and

floating point unit) with support of SDK software API faster execution of ARM CMSIS

instruction set.The PowerQuad is a hardware accelerator targeting common calculations

in DSP applications. With the assistance of the PowerQuad, the Cortex-M33 can be freed

to perform other tasks. While the PowerQuad is executing the assigned computation task,

the CM33 can prepare the next PowerQuad task, resulting in a pipeline of PowerQuad

tasks.

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