RT600 datasheet(3/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

3 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs



Two coprocessors for the Cortex-M33: a hardware accelerator for fixed and floating

point DSP functions (PowerQuad) and a Crypto/FFT engine (Casper). The DSP

coprocessor uses a bank of four dedicated 2 KB SRAMs. The Crypto/FFT engine

uses a bank of two 2 KB SRAMs that are also AHB accessible by the CPU and the

DMA engine.



Serial Wire Debug with eight break points, four watch points, and a debug

timestamp counter. It includes Serial Wire Output (SWO) trace and ETM trace.



Cortex-M33 System tick timer.



DSP processor core:



Cadence Xtensa HiFi4 Audio DSP processor, running at frequencies of up to

600 MHz.



Hardware Floating Point Unit. Up to four single-precision IEEE floating point MACs

per cycle.



Serial Wire Debug (shared with Cortex-M33 Control Domain CPU).



System tick timer.



Triple I/O power:



Three independent supplies powering different clusters of pins to permit interfacing

directly to off-chip peripherals operating at different supply levels.



On-chip Memory:



Up to 4.5 MB of system SRAM accessible by both CPUs and all (dedicated and

general purpose) DMA engines.



128 KB of local, Tightly-Coupled Memory dedicated to the DSP CPU.



96 KB (or more) of I & D cache for DSP accesses to shared system SRAM.



Additional SRAMs for USB traffic (8 KB), Cortex-M33 coprocessors (4 x 2 KB),

SDIO FIFOs (2 x 512 B dual-port), PUF secure key generation (2 KB), and FlexSPI

cache (32 KB).



16 K bits of OTP fuses for factory and user configuration.



Up to 256 KB ROM memory for factory-programmed drivers and APIs.



System boot from SPI, I2C, UART, Octal/Quad SPI Flash, HS USB or eMMC via

on-chip bootloader software included in ROM.



Digital peripherals:



Two general purpose DMA engines, each with 32 channels and up to 25

programmable request/trigger sources.

- Can be configured such that one DMA is secure and the other non-secure and/or

one can be designated for use by the M33 CPU and the other by the DSP.



USB high-speed host/device controller with on-chip PHY and dedicated DMA

controller.



FlexSPI flash interface with 32 KB cache and dynamic decryption for

execute-in-place and supports DMA. The FlexSPI includes 2 ports: high speed

channel A and lower speed channel B. Both ports support quad or octal operation.



An SD/eMMC memory card interface with dedicated DMA controller. Supports

eMMC 5.0 with HS400/DDR operation (HS-400 is supported only on SD port 0).



Eight configurable universal serial interface modules (Flexcomm Interfaces). Each

module contains an integrated FIFO and DMA support. Flexcomms 0 through 7can

be configured as:

- A USART with dedicated fractional baud rate generation and flow-control

handshaking signals. The USART can optionally be clocked at 32 kHz and

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