RT600 datasheet(46/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

46 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

PMIC_IRQ_N

A15

[2]

Z I

- Interrupt input, active low logic. Used with an off-chip PMIC, if

present.

PMIC_MODE0 -

C15

[2]

O O

- Power mode control output to an off-chip PMIC, if present.

Value is controlled by the PDRUNCFG and PDSLEEPCFG

registers. Reset state is 0.

PMIC_MODE1 -

B16

[2]

O O

- Power mode control output to an off-chip PMIC, if present.

Value is controlled by the PDRUNCFG and PDSLEEPCFG

registers. Reset state is 0.

RESETN

K10 B15

- I

- External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states, and the boot code to execute. Wakes up the part from

deep power-down mode. Minimum reset pulse width is 4ns.

RTCXIN

B17

- -

- RTC oscillator input. Selectable on-chip crystal load

capacitors are available for RTC oscillator. Please refer to UM

for further details.

RTCXOUT

A17

- -

- RTC oscillator input. Selectable on-chip crystal load

capacitors are available for RTC oscillator. Please refer to UM

for further details.

USB1_DM

T17

- I/O - USB1 bidirectional D- line.

USB1_DP

B10 R17

- I/O - USB1 bidirectional D+ line.

USB1_VBUS

[4]

R16

- I

- VBUS pin (power on USB cable). 5 V tolerant pin when

supplies are present or when not present.

USB1_VDD3V3 C10 N16

[3]

- -

- USB1 analog 3.3 V supply.

LDO_ENABLE

A16

- -

- When 1, enables the on-chip regulator to power core logic

through the VDDCORE pins. Tie low if an off-chip power

management IC (PMIC) is used to supply power to core logic.

This pin can not be left floating. 100K external pull-up or 10K

external pull-down is recommended. LDO_Enable is a

fail-safe pin. It must be driven high before VDD_AO1V8

supply comes up or at the same time.

VDD_AO1V8

L11 C13;

D13

B2; D4 [3]

- -

- Supply 1.8 V supply for “always on” features. This includes

the RTC, RESETN, LDO_ENABLE, PMIC_IRQ_N,

PMIC_MODE0, and PMIC_MODE1. See Table 5

VDDIO_0

B8;

D7;

E7;

F2;

G3;

F5; H5;

K5;M5;

N6; N8;

N10

J12;

J13;

K12;

M10;

M12;

[3]

- -

- Single 1.8 V to 3.3 V power supply for GPIOs defined as

belonging to the VDDIO_0 group. VDDIO_0, VDDIO_1, and

VDDIO_2 may be supplied at different voltage levels as

needed by the application.

VDDIO_0 supplies the following port pins: PIO0_0 to

PIO0_13; PIO1_11 to PIO1_29; and PIO2_12 to PIO2_23.

See Table 5

Table 4.

Pin description …continued

Symbol

Description

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