AT89LP2052 datasheet(33/90 Pages) ATMEL

33 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

17.4

More About Mode 1

Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits

(LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the

AT89LP2052/LP4052, the baud rate is determined by the Timer 1 overflow rate. The baud rate

is determined by the Timer 1 overflow rate. Figure 17-2 shows a simplified functional diagram of

the serial port in Mode 1 and associated timings for transmit and receive.

Transmission is initiated by any instruction that uses SBUF as a destination register. The “write

to SBUF” signal also loads a “1” into the ninth bit position of the transmit shift register and flags

the TX Control unit that a transmission is requested. Transmission actually commences at S1P1

of the machine cycle following the next rollover in the divide-by-16 counter. Thus, the bit times

are synchronized to the divide-by-16 counter, not to the “write to SBUF” signal.

The transmission begins when SEND is activated, which puts the start bit at TXD. One bit time

later, DATA is activated, which enables the output bit of the transmit shift register to TXD. The

first shift pulse occurs one bit time after that.

As data bits shift out to the right, “0”s are clocked in from the left. When the MSB of the data byte

is at the output position of the shift register, the “1” that was initially loaded into the ninth position

is just to the left of the MSB, and all positions to the left of that contain “0”s. This condition flags

the TX Control unit to do one last shift, then deactivate SEND and set TI. This occurs at the tenth

divide-by-16 rollover after “write to SBUF.”

Reception is initiated by a 1-to-0 transition detected at RXD. For this purpose, RXD is sampled

at a rate of 16 times the established baud rate. When a transition is detected, the divide-by-16

counter is immediately reset, and 1FFH is written into the input shift register. Resetting the

divide-by-16 counter aligns its roll-overs with the boundaries of the incoming bit times.

The 16 states of the counter divide each bit time into 16ths. At the seventh, eighth, and ninth

counter states of each bit time, the bit detector samples the value of RXD. The value accepted is

the value that was seen in at least 2 of the 3 samples. This is done to reject noise. In order to

reject false bits, if the value accepted during the first bit time is not 0, the receive circuits are

reset and the unit continues looking for another 1-to-0 transition. If the start bit is valid, it is

shifted into the input shift register, and reception of the rest of the frame proceeds.

As data bits come in from the right, “1”s shift out to the left. When the start bit arrives at the left

most position in the shift register, (which is a 9-bit register in Mode 1), it flags the RX Control

block to do one last shift, load SBUF and RB8, and set RI. The signal to load SBUF and RB8

and to set RI is generated if, and only if, the following conditions are met at the time the final shift

pulse is generated.

RI = 0 and

Either SM2 = 0, or the received stop bit = 1

If either of these two conditions is not met, the received frame is irretrievably lost. If both condi-

tions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. At

this time, whether or not the above conditions are met, the unit continues looking for a 1-to-0

transition in RXD.

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