AT89LP2052 datasheet(12/90 Pages) ATMEL

12 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

12.1

Idle Mode

Setting the IDL bit in PCON enters Idle mode. Idle mode halts the internal CPU clock. The CPU

state is preserved in its entirety, including the RAM, stack pointer, program counter, program

status word, and accumulator. The Port pins hold the logic states they had at the time that Idle

was activated. Idle mode leaves the peripherals running in order to allow them to wake up the

CPU when an interrupt is generated. The Timer, UART and SPI blocks continue to function dur-

ing Idle. The comparator and watchdog may be selectively enabled or disabled during Idle. Any

enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an inter-

rupt, the interrupt will immediately be serviced, and following RETI the next instruction to be

executed will be the one following the instruction that put the device into Idle.

12.2

Power-down Mode

Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops

the oscillator and powers down the Flash memory in order to minimize power consumption. Only

the power-on circuitry will continue to draw power during Power-down. During Power-down, the

power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be

retained, but the SFR contents are not guaranteed once V

CC has been reduced. Power-down

may be exited by external reset, power-on reset, or certain interrupts.

The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 µs

until after one of the following conditions has occurred: Start of code execution (after any type of

reset), or Exit from power-down mode.

12.2.1

Interrupt Recovery from Power-down

Two external interrupts may be configured to terminate Power-down mode. Pins P3.2 and P3.3

may be used to exit Power-down through external interrupts INT0 and INT1. To wake up by

external interrupts INT0 or INT1, that interrupt must be enabled and configured for level-sensi-

tive operation. If configured as inputs, INT0 and INT1 should not be left floating during Power-

down even if interrupt recovery is not used.

When terminating Power-down by an interrupt, two different wake-up modes are available.

When PWDEX in PCON is zero, the wake-up period is internally timed. At the falling edge on the

interrupt pin, Power-down is exited, the oscillator is restarted, and an internal timer begins count-

ing. The internal clock will not be allowed to propagate to the CPU until after the timer has

counted for nominally 2 ms. After the time-out period the interrupt service routine will begin. The

interrupt pin may be held low until the device has timed out and begun executing, or it may

return high before the end of the time-out period. If the pin remains low, the service routine

should disable the interrupt before returning to avoid re-triggering the interrupt.

When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the

falling edge on the interrupt pin, Power-down is exited and the oscillator is restarted. However,

the internal clock will not propagate until the rising edge of the interrupt pin. The interrupt should

be held low long enough for the selected clock source to stabilize.

12.2.2

Reset Exit from Power-down

The wake-up from Power-down through an external reset is similar to the interrupt with

PWDEX = “0”. At the rising edge of RST, Power-down is exited, the oscillator is restarted, and

an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU

until after the timer has counted for nominally 2 ms. The RST pin must be held high for longer

than the time-out period to ensure that the device is reset properly. The device will begin execut-

ing once RST is brought back low.

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