AT89LP2052 datasheet(17/90 Pages) ATMEL

17 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

14. I/O Ports

All 15 port pins on the AT89LP2052/LP4052 may be configured to one of four modes: quasi-bidi-

rectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port

modes may be assigned in software on a pin-by-pin basis as shown in Table 14-1. All port pins

default to input-only mode after reset. Each port pin also has a Schmitt-triggered input for

improved input noise rejection. During Power-down all the Schmitt-triggered inputs are disabled

with the exception of P3.2 and P3.3, which may be used to wake-up the device. Therefore P3.2

and P3.3 should not be left floating during Power-down.

14.1

Quasi-bidirectional Output

Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi-

bidirectional port can be used both as an input and output without the need to reconfigure the

port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an

external device to pull the pin low. When the pin is driven low, it is driven strongly and able to

sink a large current. There are three pull-up transistors in the quasi-bidirectional output that

serve different purposes.

One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port register for

the pin contains a logic “1”. This very weak pull-up sources a very small current that will pull the

pin high if it is left floating.

A second pull-up, called the “weak” pull-up, is turned on when the port register for the pin con-

tains a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary

source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an

Table 13-4.

IPH

– Interrupt Priority High Register

IPH = B7H

Reset Value = X0X0 0000B

Not Bit Addressable

–

PCH

–

PSH

PT1H

PX1H

PT0H

PX0H

Bit

543

Symbol

Function

PCH

Comparator Interrupt Priority High

PSH

Serial Port Interrupt Priority High

PT1H

Timer 1 Interrupt Priority High

PX1H

External Interrupt 1 Priority High

PT0H

Timer 0 Interrupt Priority High

PX0H

External Interrupt 0 Priority High

Table 14-1.

Configuration Modes for Port x, Bit y

PxM0.y

PxM1.y

Port Mode

Quasi-bidirectional

Push-pull Output

Input Only (High Impedance)

Open-Drain Output

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