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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT89LP2052 датащи(PDF) 70 Page - ATMEL Corporation |
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AT89LP2052 датащи(HTML) 70 Page - ATMEL Corporation |
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70 / 90 page  70 3547F–MICRO–6/06 AT89LP2052/LP4052 22.5 In-System Programming (ISP) The AT89LP2052/LP4052 offers a serial programming interface which may be used in place of the parallel programming interface or to program the device while in system. In this document serial programming and In-System Programming (ISP) refer to the same interface. ISP supports the same command set as parallel programming. However, during ISP command bytes are entered serially over the Serial Peripheral Interface (SPI) pins. The device connections are shown in Figure 22-21. The ISP Enable User Fuse must be enabled through Parallel Program- ming prior to entering the first ISP session. ISP itself may disable the ISP Fuse, however any changes to the ISP fuses will not take affect until the device has been powered down and up again. The programmer must take care not to accidentally disable the ISP Fuse as this will make the device unprogrammable through the serial interface. Only Parallel Programming may re- enable the fuse. Table 22-3. Parallel Flash Programming and Verification Parameters Symbol Parameter Min Max Units V PPH Programming Enable Input High Voltage 11.5 12.5 V VPPL Programming Enable Input Low Voltage -0.5 VCC V I PP Programming Enable Current 1.0 mA tPWRUP Power-on to RST High 10 µs tPOR Power-on Reset Time 2 ms t CSTP CS Setup to V PP High 10 µs tHSTL High Voltage Setting time 10 µs tCLXH CS Low to XTAL1 High 100 ns t XTH XTAL1 High Width 125 ns tXTL XTAL1 Low Width 75 ns tDSTP Data Setup to XTAL1 High 50 ns t DHLD Data Hold after XTAL1 High 50 ns tXLDO XTAL1 Low to Data Out 20 ns tXLDV XTAL1 Low to Data Valid 100 ns t XLCH XTAL1 Low to CS High 100 ns tCHDZ CS High to Data Tri-state 20 ns tCHBL CS High to BUSY Low 3 µs t WRC Write Cycle Time 4.5 ms tERS Erase Cycle Time 9 ms t BHPG BUSY High to Next Erase/Write 3 µs t BHHl BUSY High to V PP Off 10 µs tCLRL CS Low to RST Low 1 µs t PWRDN RST Low to Power Off 1 µs |
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