MCP3910 datasheet(75/90 Pages) MICROCHIP

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 2012-2020 Microchip Technology Inc.

DS20005116D-page 75

MCP3910

9.7

CONFIG1 Register –

Configuration Register 1

Name

Bits

Address

Cof

CONFIG1

0x0E

R/W

CONFIG1: CONFIGURATION REGISTER 1

U-0

R/W-0

—

RESET[1]

RESET[0]

bit 23

bit 16

U-0

R/W-0

—

SHUTDOWN[1] SHUTDOWN[0]

bit 15

bit 8

R/W-0

R/W-1

U-0

VREFEXT

CLKEXT

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-18

Unimplemented:

Read as ‘0’

bit 17-16

RESET[1:0]:

Soft Reset Mode Setting for Each Individual ADC bits

= Channel CHn is in Soft Reset mode

= Channel CHn is not in Soft Reset mode

bit 15-10

Unimplemented:

Read as ‘0’

bit 9-8

SHUTDOWN[1:0]:

Shutdown Mode Setting for Each Individual ADC bits

= ADC Channel is in Shutdown mode

= ADC Channel is not in Shutdown mode

bit 7

VREFEXT:

Internal Voltage Reference Selection bit

= Internal voltage reference disabled; an external reference voltage needs to be applied across the

REFIN+/- pins; the analog power consumption (AIDD) is slightly diminished in this mode since the

internal voltage reference is placed into Shutdown mode

= Internal reference enabled; for optimal accuracy, the REFIN+/OUT pin needs proper decoupling

capacitors, REFIN- pin should be connected to AGND when in this mode

bit 6

CLKEXT:

Internal Clock Selection bit

= MCLK is generated externally and should be provided on the OSC1 pin; the crystal oscillator is

disabled and consumes no current (default)

= Crystal oscillator is enabled; a crystal must be placed between OSC1 and OSC2 with proper

decoupling capacitors; the digital power consumption (DIDD) is increased in this mode due to the

oscillator

bit 5-0

Unimplemented:

Read as ‘0’

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