MCP3910 datasheet(35/90 Pages) MICROCHIP

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DS20005116D-page 35

MCP3910

Equation 5-1 calculates the filter z-domain transfer

function.

EQUATION 5-1:

SINC FILTER TRANSFER

FUNCTION

Equation 5-2 calculates the settling time of the ADC as

a function of DMCLK periods.

EQUATION 5-2:

The SINC1 filter following the SINC3 filter is only

enabled for the high OSR settings. This SINC1 filter

provides additional rejection at a low cost with little

modification to the -3 dB bandwidth. The resolution

(number of significant bits) of the digital filter is a 24-bit

maximum for any OSR and data format choice. The

resolution depends only on the OSR[2:0] settings in the

CONFIG0 register per Table 5-4. Once the OSR is

chosen, the resolution is fixed and the output code

respects

the

data

format

defined

the

WIDTH_DATA[1:0] setting in the STATUSCOM register

(see Section 5.5 “ADC Output Coding”).

The gain of the transfer function of this filter is one at each

multiple of DMCLK (typically 1 MHz), so a proper

anti-aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the con-

verter. This anti-aliasing filter can be a simple, first-order

RC network, with a sufficiently low time constant to

generate high rejection at the DMCLK frequency

Any unsettled data are automatically discarded to avoid

data corruption. Each data ready pulse corresponds to

fully settled data at the output of the decimation filter.

The first data available at the output of the decimation

filter are present after the complete settling time of the

filter (see Table 5-4). After the first data have been

processed, the delay between two data ready pulses is

one DRCLK period. The data stream from input to out-

put is delayed by an amount equal to the settling time

of the filter (which is the group delay of the filter).

The resolution achievable, the -3 dB bandwidth and the

settling time at the output of the decimation filter (the

output of the ADC) are dependent on the OSR of each

SINC filter and are summarized in Table 5-4.

FIGURE 5-4:

SINC Filter Frequency

Response, OSR = 256, MCLK = 4 MHz,

PRE[1:0] = 00.

FIGURE 5-5:

SINC Filter Frequency

Response, OSR = 4096 (in pink), OSR = 512 (in

blue), MCLK = 4 MHz, PRE[1:0] = 00.



- OSR

–





OSR

1z 1

–



3

----------------------------------------------

- OSR

OSR



–





OSR

- OSR

–







---------------------------------------------------------



Where z

EXP 2

 jf



 DMCLK







Sett lingTi me DMCLKperiods

 3OSR



OSR

–

 OSR



TABLE 5-4:

OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME

OSR[2:0]

OSR3

OSR1

Total OSR

Resolution in Bits

(No Missing Code)

Settling Time

-3 dB Bandwidth

000

96/DMCLK

0.26*DRCLK

001

192/DMCLK

0.26*DRCLK

010

128

384/DMCLK

0.26*DRCLK

011

256

768/DMCLK

0.26*DRCLK

100

512

1536/DMCLK

0.26*DRCLK

101

512

1024

2048/DMCLK

0.37*DRCLK

110

512

2048

3072/DMCLK

0.42*DRCLK

111

512

4096

5120/DMCLK

0.43*DRCLK

-80

-60

-40

-20

-120

-100

100

1000

10000

100000

Input Frequency (Hz)

-100

-80

-60

-40

-20

-160

-140

-120

100

10000

1000000

Input Frequency (Hz)

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