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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCP3910 датащи(PDF) 24 Page - Microchip Technology |
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MCP3910 датащи(HTML) 24 Page - Microchip Technology |
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24 / 90 page  MCP3910 DS20005116D-page 24 2012-2020 Microchip Technology Inc. 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device, after prescaling and division by four (Equation 4-2). This is also the sampling frequency, which is the rate at which the modulator outputs are refreshed. Each period of this clock corre- sponds to one sample and one modulator output. See Figure 4-1. EQUATION 4-2: 4.4 DRCLK – Data Rate Clock This is the output data rate (i.e., the rate at which the ADCs output new data). Each new data are signaled by a data ready pulse on the DR pin. This data rate is dependent on the OSR and the prescaler with the formula in Equation 4-3. EQUATION 4-3: Since this is the output data rate, and because the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. Table 4-2 describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates. DMCLK AMCLK 4 --------------------- MCLK 4PRESCALE ---------------------------------------- == DRC LK DMC LK OSR ---------------------- AMCLK 4OSR --------------------- MCLK 4 OSR PRESCALE ----------------------------------------------------------- == = |
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