MCP3910 datasheet(29/90 Pages) MICROCHIP

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DS20005116D-page 29

MCP3910

4.19

ADC Reset Mode

ADC Reset mode (also called Soft Reset mode) can

only be entered in SPI mode through setting the

RESET[1:0] bits high in the CONFIG1 register. This

mode is defined as the condition where the converters

are active, but their output is forced to ‘0’.

The registers are not affected in this Reset mode and

retain their state, except the data registers of the

corresponding channel, which are reset to ‘0’.

The ADCs can immediately output meaningful codes

after leaving the Reset mode (and after the SINC filter

settling time). This mode is both entered and exited

through bit settings in the CONFIG1 register.

Each converter can be placed in Soft Reset mode

independently. The Configuration registers are not

modified by the Soft Reset mode. A data ready pulse

will not be generated by any ADC in Reset mode.

When an ADC exits ADC Reset mode, any phase delay

present before Reset was entered will still be present. If

one ADC was not in Reset, the ADC leaving the Reset

mode will automatically resynchronize the phase delay

relative to the other ADC channel per the Phase Delay

If an ADC is placed in Reset mode while the other is

converting, it does not shut down the internal clock.

When coming out of Reset, it will be automatically

resynchronized with the clock, which did not stop

during Reset.

However, when the two channels are in Soft Reset, the

input structure is still clocking if MCLK is applied in

order to properly bias the inputs, so that no leakage

current is observed. If MCLK is not applied, large

analog input leakage currents can be observed for

highly negative input voltages (typically, below -0.6V,

referred to as AGND).

4.20

Hard Reset Mode (RESET = 0)

This mode is only available during a POR or when the

RESET pin is pulled low in SPI mode. The RESET pin

logic low state places the device in Hard Reset mode.

In this mode, all internal registers are reset to their

default state. In the Two-Wire Interface mode, the

RESET pin functionality is not available and the user

must use a Watchdog Timer Reset to be able to fully

reset the part (see Section 7.4 “Watchdog Timer

Reset, Resetting the Part in Two-Wire Mode”

The DC biases for the analog blocks are still active (i.e.,

the MCP3910 is ready to convert). However, this pin

clears all conversion data in the ADCs. The comparators’

outputs of all ADCs are forced to their Reset state

(‘0011’). The SINC filters are all reset, as well as their

double-output buffers. See serial timing for minimum

pulse low time in Section 1.0 “Electrical Characteris-

tics”

. During a Hard Reset, no communication with the

part is possible. The digital interface is maintained in a

Reset state.

During this state, the clock MCLK can be applied to the

part in order to properly bias the input structures of all

channels. If not applied, large analog input leakage cur-

rents can be observed for highly negative input signals

and, after removing the Hard Reset state, a certain

start-up time is necessary to bias the input structure

properly. During this delay, the ADC conversions can

be inaccurate.

4.21

ADC Shutdown Mode

ADC Shutdown mode is defined as a state where the

converters and their biases are off, consuming only

leakage current. When the SHUTDOWN bit is reset to

‘0’, the analog biases will be enabled, as well as the

clock and the digital circuitry. The ADC will give a data

ready pulse after the SINC filter settling time has

occurred. However, since the analog biases are not

completely settled at the beginning of the conversion,

the sampling may not be accurate for about 1 ms (cor-

responding to the settling time of the biasing under

worst-case conditions). In order to ensure accuracy,

the data ready pulse within the delay of 1 ms + settling

time of the SINC filter should be discarded.

Each converter can be placed in Shutdown mode

independently. The Configuration registers are not

modified by the Shutdown mode. This mode is only

available in SPI mode through programming the

SHUTDOWN[1:0] bits of the CONFIG1 register.

The output data are flushed to all zeros while in ADC

Shutdown mode. No data ready pulses are generated

by any ADC while in ADC Shutdown mode.

When an ADC exits ADC Shutdown mode, any phase

delay present before Shutdown was entered will still be

present. If one ADC was not in Shutdown, the ADC

leaving Shutdown mode will automatically resynchro-

nize the phase delay, relative to the other ADC

channel, per the Phase Delay register block and will

give data ready pulses accordingly.

If an ADC is placed in Shutdown mode while the other

is converting, it is not shutting down the internal clock.

When coming out of shutdown, it will be automatically

resynchronized with the clock that did not stop during

Reset.

If all ADCs are in ADC Shutdown mode, the clock is not

distributed to the input structure or to the digital core for

low-power operation. This can potentially cause high

analog input leakage currents at the analog inputs if the

input voltage is highly negative (typically, below -0.6V,

referred to as AGND). Once either of the ADCs is back

to normal operation, the clock is automatically distributed

again.

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