MCP3910 datasheet(56/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 56

 2012-2020 Microchip Technology Inc.

7.2

Two-Wire Mode Configuration

Settings

When the user wants to exclusively use the Two-Wire

Interface mode in digitally isolated applications, the

OSC2 pin should always be in a logic high state,

starting from the power-up of the part. Otherwise, the

user can change the interface mode by toggling the

OSC2/MODE pin within a POR, a Hard Reset or a

Watchdog Timer Reset; the MODE is latched when

exiting one of these three types of Reset. When the part

has entered Two-Wire mode, the entire part configura-

tion keeps its default settings (see Section 9.0

“MCP3910 Internal Registers”

for the default settings

of all internal registers), except for the configuration of

the Gain in Channel 0, the OSR and the BOOST

settings.

In Two-Wire Interface mode, the input pins,

OSR0/OSR1/BOOST/GAIN0/GAIN1, are latched on

the OSC2/MODE rising edge and should typically be

directly connected to DVDD or DGND, depending on the

desired configuration. These pins define the only

configurable settings in Two-Wire mode. If more set-

tings are required by the application, it is recommended

to use the SPI mode. The following tables describe the

configuration options for these five pins.

7.2.1

OSR1/OSR0

OSR Setting Logic pins. These inputs are Schmitt

triggered.

7.2.2

BOOST

Current Boost Setting Logic pin. This input is Schmitt

triggered.

7.2.3

GAIN1/GAIN0

Channel 0 Gain Setting Logic pins. These inputs are

Schmitt triggered.

7.3

Two-Wire Communication

Protocol

In Two-Wire mode, the SCK/MCLK pin needs to be

clocked continuously at all times for proper operation.

Any change in the clock frequency will lead to

degraded THD/SFDR specifications. The part obeys

the same timing specifications in both SPI and

Two-Wire Interface mode for the SCK/SDO pins. The

MCLK maximum input frequency is 10 MHz in

Two-Wire mode, since the converter still respects

Table 5-2 for maximum AMCLK frequency (provided

the part has entered Two-Wire mode at power-up).

Since the MCLK is divided internally, the part accepts a

wide range of duty cycles for the SCK input, provided

the serial interface timings are respected.

In Two-Wire Interface mode, communication uses

framed data sets on the SDO to output data at a fixed

data rate, synchronously with SCK, and using only one

output pin. The frame is different depending on the

device and the Oversampling Ratio (OSR) selected.

When in OSR = 64 mode, the MCP3910 frame contains

the sync bytes (16-bit), two channels of 16-bit ADC data

and a 16-bit CRC. For OSR = 128 and higher, each

frame is a group of ten bytes (80 bits) clocked by the

Serial Clock, SCK. Each frame is composed of a sync

word (two bytes), 24-bit data output words (three bytes)

for both channels and a 16-bit CRC. The sync word

comes first, followed by Channel 0 ADC output

(DATA_CH0[23:0]),

Channel

ADC

output

(DATA_CH1[23:0])

and

the

16-bit

CRC

(see

Figure 7-1 and Figure 7-2).

As a verification feature, the sync word contains all set-

tings coming from the five logic input pins available

(OSR0/1, GAIN0/1, BOOST) in order to provide the

user with the information about this configuration. It

also provides information about the count of the frame

through bits, CNT0/1, which is useful when the SDO is

multiplexed at the output of the digital isolators (see

next paragraph). The sync word also contains an addi-

tional sync byte (fixed at the 0xA5 value) for additional

security in synchronization and communication.

TABLE 7-1:

OSR SETTINGS

OSR1

OSR0

OSR

128

256

512

TABLE 7-2:

CURRENT BOOST SETTINGS

BOOST Pin

Boost

0.5x

TABLE 7-3:

CHANNEL 0 GAIN SETTINGS

GAIN1

GAIN0

CH0 PGA GAIN

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