MCP3910 datasheet(50/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 50

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6.5.2

CONTINUOUS WRITE

For the Continuous Write modes, the address selection

can take the two following values:

SDO is always in a high-impedance state during a con-

tinuous write communication. Writing to a non-writable

address (such as addresses: 0x00 to 0x07, or any of

the unused register’s addresses) has no effect and

does not increment the Address Pointer. In this case,

the user needs to stop the communication and restart a

communication with a control byte pointing to a writable

address (0x08 to 0x1F).

6.6

Situations that Reset and Restart

Active ADCs

Immediately after the following actions, the active

ADCs (the ones not in Soft Reset or Shutdown modes)

are reset and automatically restarted in order to provide

proper operation:

Change in PHASE register.

Overwrite of the same PHASE register value.

Change in the OSR[2:0] settings.

Change in the PRE[1:0] settings.

Change in the CLKEXT setting.

Change in the VREFEXT setting.

After these temporary Resets, the ADCs go back to

normal operation with no need for an additional

command. Each ADC Data Output register is cleared

during this process. The PHASE register can be used

to serially soft reset the ADCs, without using the

RESET[1:0] bits in the Configuration register, if the

same value is written in the PHASE register.

6.7

Data Ready Pin (DR)

To communicate when channel data are ready for

transmission, the data ready signal is available on the

Data Ready pin (DR) at the end of a channel conver-

sion. The Data Ready pin outputs an active-low pulse

with a pulse width equal to half a DMCLK clock period.

After a data ready pulse falling edge has occurred, the

ADC output data are updated within the tDODR timing

and can then be read through SPI communication.

The first data ready pulse after a Hard or a Soft Reset

is located after the settling time of the SINC filter (see

Table 5-4) plus the phase delay of the corresponding

channel (see Section 5.9 “Phase Delay Block”).

Each subsequent pulse is then periodic, and the period

is equal to a DRCLK clock period (see Equation 4-3

and Figure 1-3). The data ready pulse is always

synchronous with the internal DRCLK clock.

The DR pin can be used as an interrupt pin when

connected to an MCU or DSP, which will synchronize

the readings of the ADC data outputs. When not

active-low, this pin can either be in high-impedance

(when DR_HIZ = 0) or in a defined logic high state

(when DR_HIZ = 1). This is controlled through the

STATUSCOM register. This allows multiple devices to

share the same Data Ready pin (with a pull-up resistor

connected between DR and DVDD). If only the

MCP3910 device is connected on the interrupt bus, the

DR pin does not require a pull-up resistor, and therefore,

it is recommended to use the DR_HIZ = 1 configuration

for such applications.

The CS pin has no effect over the DR pin, which means

even if the CS pin is logic high, the data ready pulses

coming from the active ADC channels will still be pro-

vided; the DR pin behavior is independent from the SPI

interface. While the RESET pin is logic low, the DR pin

is not active. The DR pin is latched in the logic low state

when the interrupt flag on the CRCREG is present to

signal that the desired register configuration has been

corrupted (see Section 6.11 “Detecting Configuration

Change through CRC-16 Checksum on Register

Map and its Associated Interrupt Flag”

TABLE 6-2:

ADDRESS SELECTION IN

CONTINUOUS WRITE

WRITE

Continuous Write Communications

Static (no incrementation)

Types (Default)

Note:

When the LOCK[7:0] bits are different than

0xA5, all the addresses, except 0x1F,

become non-writable (see Section 6.10,

Locking/Unlocking Register Map Write

Access

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