MCP3910 datasheet(43/90 Pages) MICROCHIP

43 / 90 page

 2012-2020 Microchip Technology Inc.

DS20005116D-page 43

MCP3910

5.13

Digital System Offset and Gain

Errors

The MCP3910 incorporates two sets of additional

registers per channel to perform system digital offset and

gain error calibration. Each channel has its own set of

associated registers that will modify the output result of

the channel if calibration is enabled. The gain and offset

calibrations can be enabled or disabled through two

Configuration bits (EN_OFFCAL and EN_GAINCAL).

These two bits enable or disable system calibration on

all channels at the same time. When both calibrations

are enabled, the output of the ADC is modified per

Equation 5-8. These calibrations are not effective in

Two-Wire Interface mode.

EQUATION 5-8:

DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS

CALCULATIONS

5.13.1

DIGITAL OFFSET ERROR

CALIBRATION

The

23-bit

OFFCAL_CHn

registers

are

two’s

complement registers whose LSB value is the same as

the channel ADC data. These two registers are then

added, bit by bit, to the ADC output codes if the

EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL

bit does not create a pipeline delay; the offset addition

is instantaneous. For low OSR values, only the

significant digits are added to the output (up to the

resolution of the ADC; for example, at OSR = 32, only

the 17 first bits are added).

The offset is not added when the corresponding

channel is in Reset or Shutdown mode. The

corresponding input voltage offset value added by each

LSB in these 24-bit registers is:

EQUATION 5-9:

These registers are “Don’t Care” if EN_OFFCAL = 0

(offset calibration disabled), but their value is not

cleared by the EN_OFFCAL bit.

5.13.2

DIGITAL GAIN ERROR

CALIBRATION

This register is a 24-bit signed MSB first coding, with

a range of -1x to +0.9999999x (from 0x80000 to

0x7FFFFF). The gain calibration adds 1x to this

channel, bit by bit, after offset calibration. The range of

the gain calibration is thus from 0x to 1.9999999x (from

0x80000 to 0x7FFFFF). The LSB corresponds to a 2-23

increment in the multiplier.

Enabling EN_GAINCAL creates a pipeline delay of

24 DMCLK periods on all channels. All data ready

pulses are delayed by 24 DMCLK periods, starting from

data ready following the command enabling the

EN_GAINCAL bit. The gain calibration is effective on

the next data ready following the command enabling

the EN_GAINCAL bit.

The digital gain calibration does not function when the

corresponding channel is in Reset or Shutdown mode.

The gain multiplier value for an LSB in these 24-bit

registers is:

EQUATION 5-10:

This register is a “Don’t Care” if EN_GAINCAL = 0

(offset calibration disabled), but its value is not cleared

by the EN_GAINCAL bit.

The output data on each channel are kept to either

7FFF or 8000 (16-bit mode), or 7FFFFF or 800000

(24-bit mode) if the output results are out of bounds

after all calibrations are performed.

DATA_CHn post

cal

–



DATA_CHn pre

cal

–

 OFFCAL_CHn



GAINCAL_CHn





OFFSET(1 LSB) = VREF/(PGA_CHn x 1.5 x 8388608)

GAIN (1 LSB) = 1/8388608

MCP3910 датащи(PDF) 43 Page - Microchip Technology

MCP3910 датащи(HTML) 43 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

датащи скачать

ссылки URL