CS4525 datasheet(28/91 Pages) CIRRUS

28 / 91 page

DS726A1

CS4525

6.1.2

Power-Up and Power-Down

The CS4525 will remain in a completely powered-down state with the control port inaccessible until the

RST pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks

will remain powered-down until they are powered-up via the control port or until hardware mode is en-

tered.

When an external crystal is present on the XTI/XTO pins, software mode will be automatically entered

10 ms after the release of RST. If SYS_CLK is used as an input, software mode is entered by writing to

the control port within 10 ms after the release of RST. If the control port is not written within this time, the

device will begin to operate in hardware mode.

6.1.2.1

Recommended Power-Up Sequence

Hold RST low until the power supplies and the input SYS_CLK (if used) are stable.

Bring RST high.

The device will remain in a low-power state and the control port will be accessible. The device will

automatically enter software mode after 10 ms if an external crystal is present on the XTI/XTO pins,

at which time the output SYS_CLK signal will become active.

If SYS_CLK is used as an input, initiate a control port write to set the PDnAll bit in register 5Fh within

10 ms following the release of RST.

This operation causes the device to enter software mode and places it in power-down mode.

If the LVD pin is tied low and VD is connected to 2.5 V, clear the SelectVD bit in the Power Ctrl register

to indicate the 2.5 V VD supply level.

The desired register settings can be loaded while keeping the PDnAll bit set.

Clear the PDnAll bit to initiate the power-up sequence.

6.1.2.2

Recommended Power-Down Sequence

Set the PDnAll bit to power-down the device while eliminating audible pops.

Bring RST low to bring the device’s power consumption to an absolute minimum.

Remove power.

6.1.3

Input Source Selection

The CS4525 can accept analog or digital audio input signals. Digital audio input signals are supplied

through the serial audio input port as outlined in “Serial Audio Interfaces” on page 57. Analog audio input

signals are supplied through the internal ADC as outlined in “Analog Inputs” on page 56. The input source

is selected by the ADC/SP bit in the Input Config register.

In software mode, the serial audio input port supports I²S, Left-Justified and Right-Justified data formats.

The serial audio input port digital interface format is configured by the DIF[2:0] bits in the Input Config reg-

ister.

The CS4525 internal ADC includes a dedicated high-pass filter to remove any DC content from the ADC

output signal prior to the internal ADC/serial audio input port input multiplexor. This high-pass filter can be

bypassed by clearing the EnAnHPF bit.

Referenced Control

PDnAll ................................. “Power Down (PDnAll)” on page 81

LVD ..................................... “Select VD Level (SelectVD)” on page 81

Referenced Control

ADC/SP............................... “Input Source Selection (ADC/SP)” on page 66

DIF[2:0] ............................... “Input Serial Port Digital Interface Format (DIF [2:0])” on page 66

EnAnHPF ............................ “ADC High-Pass Filter Enable (EnAnHPF)” on page 66

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