CS4525 datasheet(6/91 Pages) CIRRUS

6 / 91 page

DS726A1

CS4525

9.18.1 Select VD Level (SelectVD) ................................................................................................. 81

9.18.2 Power Down ADC (PDnADC) .............................................................................................. 81

9.18.3 Power Down PWM Power Output X (PDnOutX) .................................................................. 81

9.18.4 Power Down (PDnAll) .......................................................................................................... 81

9.19 Interrupt Register (Address 60h) ................................................................................................. 82

9.19.1 SRC Lock State Transition Interrupt Bit (SRCLock) ............................................................. 82

9.19.2 ADC Overflow Interrupt Bit (ADCOvfl) ................................................................................. 82

9.19.3 Channel Overflow Interrupt Bit (ChOvfl) ............................................................................... 82

9.19.4 Amplifier Error Interrupt Bit (AmpErr) ................................................................................... 83

9.19.5 Mask Bit for SRC State (SRCLockM) ................................................................................... 83

9.19.6 Mask Bit for ADC Overflow (ADCOvflM) .............................................................................. 83

9.19.7 Mask Bit for Channel X Overflow (ChOvflM) ........................................................................ 84

9.19.8 Mask Bit for Amplifier Error (AmpErrM) ................................................................................ 84

9.20 Interrupt Status Register (Address 61h) - Read Only .................................................................. 84

9.20.1 SRC State Transition (SRCLockSt) ..................................................................................... 84

9.20.2 ADC Overflow (ADCOvfl) ..................................................................................................... 85

9.20.3 Channel X Overflow (ChXOvfl) ............................................................................................85

9.20.4 Ramp-Up Cycle Complete (RampDone) .............................................................................. 85

9.21 Amplifier Error Status (Address 62h) - Read Only ....................................................................... 85

9.21.1 Over-Current Detected On Channel X (OverCurrX) ............................................................. 85

9.21.2 External Amplifier State (ExtAmpSt) .................................................................................... 86

9.21.3 Under Voltage Detected (UnderV) ....................................................................................... 86

9.21.4 Thermal Error Detected (ThermErr) ..................................................................................... 86

9.21.5 Thermal Warning Detected (ThermWarn) ............................................................................ 86

9.22 Chip I.D. and Revision Register (Address 63h) - Read Only ....................................................... 87

9.22.1 Device Identification (DeviceID[4:0]) .................................................................................... 87

9.22.2 Device Revision (RevID[2:0]) ............................................................................................... 87

10. PARAMETER DEFINITIONS .............................................................................................................. 88

11. REFERENCES .................................................................................................................................... 88

12. PACKAGE DIMENSIONS .................................................................................................................. 89

13. THERMAL CHARACTERISTICS ....................................................................................................... 90

13.1 Thermal Flag ............................................................................................................................... 90

14. ORDERING INFORMATION .............................................................................................................. 90

15. REVISION HISTORY .......................................................................................................................... 91

LIST OF FIGURES

Figure 1.Typical Connection Diagram - Software Mode ........................................................................... 13

Figure 2.Typical Connection Diagram - Hardware Mode .......................................................................... 14

Figure 3.Typical System Configuration 1 .................................................................................................. 15

Figure 4.Typical System Configuration 2 .................................................................................................. 15

Figure 5.Typical System Configuration 3 .................................................................................................. 16

Figure 6.Typical System Configuration 4 .................................................................................................. 17

Figure 7.Serial Audio Input Port Timing .................................................................................................... 21

Figure 8.AUX Serial Port Interface Master Mode Timing ..........................................................................22

Figure 9.SYS_CLK Timing from Reset ..................................................................................................... 23

Figure 10.PWM_SIGX Timing ................................................................................................................... 23

Figure 11.Control Port Timing - I²C ........................................................................................................... 24

Figure 12.Typical SYS_CLK Input Clocking Configuration ....................................................................... 26

Figure 13.Typical Crystal Oscillator Clocking Configuration ..................................................................... 27

Figure 14.Digital Signal Flow .................................................................................................................... 29

Figure 15.De-Emphasis Filter ................................................................................................................... 31

Figure 16.Bi-Quad Filter Architecture ........................................................................................................ 33

Figure 17.Peak Signal Detection & Limiting .............................................................................................. 37

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